资源列表
hanbaosram
- 德国汉堡大学的SRAM测试代码,使用VHDL编写,供大家参考-University of Hamburg, Germany, SRAM test code, the use of VHDL, for your reference
ramrw
- 一个用外部ＭＣＵ通过ＦＰＧＡ来访问外部ＲＡＭ的文件-an external MCU used by FPGA to access external RAM documents
compbijiaoqi
- 一个比较器的实现方法，方法比较简单，作为大家设计时的参考-a comparison of the method is relatively simple method, as we design reference
fir_filter
- 常系数的FIR滤波器VHDL设计文件，在MUX+plusII调试通过-regular FIR filter coefficients of VHDL design documents, the debugging through MUX plusII
Viterbidecoder
- 维特比解码器低功耗设计verilog编码完整的程序可直接用-Viterbi decoder low power design Verilog coding complete procedures can be used directly
sl.v
- 路灯控制器 采用了状态机的概念编程，其中采用了信号检测进程防止干扰信号驱动芯片工作-lights controller state machine used the concept of programming, where the signal detection processes to prevent signal interference driver chips work
PLDESIGNQA91
- 这是硬件逻辑设计的一份参考资料，总结了目前主流FPGA供应商设计的注意事项。-This is a hardware logic design of a reference, summed up the current mainstream FPGA vendor design for attention.
ping_pang
- 这是用AHDL语言编写的一个PCI采集系统的逻辑源码，其中的乒乓设计思路新颖，有兴趣的朋友可以参考一下！编译环境为maxplus2-This is AHDL prepared a PCI Acquisition System logical source, the Table Tennis novel design concept, interested friends can take a look! Build environment for maxplus2
ddfs
- 我自己用vhdl实现编的dds，能实现正弦波，方波，三角波。-my own use VHDL to achieve series dds, able sine, square, triangle wave.
ccccc
- 串口通讯的例子 串口通讯的例子-examples of serial communications example s of serial communications serial communications examples examples of serial communications
Comparators_16B
- verilog 实现 优化的16位比较器 可以输出大于，小于，等于。模块化设计，可扩展为32位-Verilog achieve optimization of 16 compared with the output can be greater than, less than, equal to. Modular design, which can be expanded to 32
QuartusII3.0
- QuartusII 3.0学习教程 ，chm文件，经典-study guides, chm, classic