资源列表
VHDL
- 基于VHDL语言和CPLD开发板的，分频电路电路的开发。-Based on VHDL and CPLD development board, divider circuit circuit development.
cell_arch
- cell architecture for dual port ram
triangle
- 这是用vhdl编写的三角波产生程序，比较简单，但是对于开发学者的思维还是有帮助的。当时我受益颇多，拿出分享。-This is a program used to generate the triangular wave vhdl written, relatively simple, but for the development of academic thinking is helpful. At that time, I benefited a lot, come to share.
SingleclocksynchronousdesignmetricCNTR
- 用VHDL 设计的单时钟同步十进制可逆计数器的设计-VHDL design using a single clock synchronization decimal CNTR Design
mux2_1
- 2选1数据选择器，用于数据的切换，vhdl编写，实际使用过-mux2 to 1
4ask
- 数字通信系统4进制振幅键控4ASK信号的调制的VHDL代码-Digital Communication Systems 4 binary amplitude shift keying modulation 4ASK signal VHDL code
screen_1
- 符合avalon总线接口的LED控制软核-Avalon bus interface LED control soft-core
wsm
- 八位数码管的位扫描程序，已在开发板上验证使用-Digital tube scanner, has been verified on the development board to use
counter8
- 8 位 计数器，带使能键和重置键。附带testbench, verilog 环境-8 bit counter
m_serial
- m序列产生。3个300阶m序列级联，产生近似随机的数数。输出包括串行输出的随机时钟和并行输出的32位的随机数。-m sequence generation. 3 300 m-order sequence cascade, resulting in an approximate number of random numbers. Output 32 of the random numbers and the parallel clock output comprises serial output
mux
- 二选一数据选择器，可以实现在两个数据中选择一个数据的功能。-Choose one data selector can a data in two data functions.
behavioral-hmwk5
- Design a synchronous circuit which monitors a 3-bit code as the input. If the code has a constant value in four consecutive clock cycles, a flag is activated.