资源列表
Encoder8_3
- this is a source code for 3 is to 8 decoder
binary_adder_subtractor
- binary adder / subtracter in vhdl
4bitmultiplier
- its a verilog coding of a multiplier. it multiply 2 values each of width having 4bit
fifo
- A First in first out buffer in Verilog
dds
- da的代码,在VHDL的编译环境下的开发。是一种集约的形式。-DA convert
pwm
- VHDL编写的PWM波控制LED亮度的程序。-Written in VHDL wave PWM LED brightness control procedures.
OR_gate
- VHDL OR gate source code
ram
- 一个简单的ram，自己写的。希望对大家有用-A simple ram, write your own. Hope to useful
counter
- module counter for VHDL on FPGA Kit
8-way-control-lantern
- 8路移存型彩灯题目要求两种花型，本次实验分别实现这两种花型，它的设计主要采用74194接成扭环形结构的移位寄存器来实现，整个电路主要由编码发生器、控制电路、脉冲发生器构成可以实现控制8个以上的彩灯，并且可以组成多种花型。 -8 subject lantern-type shift registers require two flower type, respectively, the experimental realization of the two flower types, it i
leftrotate
- VHDL code of left rotate
VGA
- VGA时序verilog hdl，实现显示器vga接口的控制，-VGA timing verilog hdl, vga interface to achieve the display control