资源列表
leijiaqi
- 从000000000到11111111其中步进为K（随便设，）逐步增加，每遇到上升沿时进行增加-One step from 000,000,000 to 11,111,111 for the K (casual set,) and gradually increased to increase when the rising edge of each encounter
lab1
- 本实验主要设计基本的门电路，包括两输入与门，两输入与非门，两输入或门，两输入 或非门，两输入异或门，两输入同或门。-In this study, the basic design of the main gates, including two input AND gate, two input NAND gate, two input OR gate, the two input NOR gate, the two input XOR gate with two input OR gate
www
- 主要功能就是实现基于FPGA的FIR滤波器设计的串并转换。-Main function is to implement FPGA-based FIR filter design and convert the string.
fp-exam
- FPGA基本实验，用verilog实现蜂鸣器的响灭控制，每隔一段时间蜂鸣器响-FPGA basic experimental verilog achieve buzzer rang off control, and from time to time buzzer
vga control
- This tutorial familiarizes you with the Nios® II Software Build Tools (SBT) for Eclipse and the MicroC/OS-II development flow. The Nios II SBT for Eclipse offers designers a rich development platform for Nios II applications. The Nios II SBT for Ecli
internal_reset.v
- code for internal reset in fpga
hardreg
- a simple flip flop to understand verilog code
mux
- the multiplexer program are designed 2:1 and 4:1 in verilog model
DECIMAL_COUNTER
- decimal counter to start from 0 to 10 decimal up
ls74160
- VHDL设计的160集成电路，仿真测试正确，可以使用。-160 IC VHDL design, simulation tests correctly, can be used.
4位乘法累加器
- 4位乘法累加器，有需要的下吧，其他位的可以自行修改~-Multiplication accumulator 4
eightbitLatch
- 一种8位锁存器，程序简单，为初学者提供，一种简单的数据锁存方式。-a kind of eight bits latch。