资源列表
12_sdram
- 黑金开封版配套程序12，定时器的程序。与大家分享一下-Black Gold Kaifeng version supporting program 12 timer programs. Share with you
FTCTRL
- 四位十进制频率计的顶层控制模块，用于生成测频需要的复位及控制信号-four decimal frequency of top-level control modules, used to generate the required frequency measurement and control signals reset
DataConverter
- 利用VHDL语言实现8位到32位的双向数据转换-use VHDL 8-32 two-way data conversion
fq_divider
- 分频器-Divider ..
BUFG_CLK2X_FB_SUBM
- xilinx DCM 应用的源代码，完全可用-xilinx DCM application source code, fully available
fpga_led_clock
- 最近用verilog编写的数字时钟显示代码，已在FPGA开发板上跑过。-Recently prepared with digital clock display verilog code ran in FPGA development board.
disply
- 硬件描述语言，点亮7位数码管，能实现数据的接收并显示。-Hardware descr iption language, lit seven digital tube, to achieve data reception and display.
CPLDfrequency
- 频率计CPLD模块。主要实现多次十分频，对各位频率进行计数。锁存和清零功能-Frequency counter:function as a frequency division. counter each bit. latch and clear
fifo_interface
- vdsp w5300 可以扩展很多种应用-vdsp w5300
RT.v
- B61580 1553B RT模式配置,芯片驱动控制程序-B61580 1553B RT
NRZ_2_Manchester
- NRZ码到Manchester转换器 verilog
liftbd53
- 小波提升算法5_3 verilog 源码-Wavelet lifting algorithm 5_3 verilog source