资源列表
BUFG_CLK0_FB_SUBM
- xilinx DCM 应用程序，完全可用-xilinx DCM applications, fully available
fifo
- 毕设做的fifo存储器的代码 希望对大家有用
MCU_PORT
- VHDL编写的用于和CPU接口的程序，简单明了，一用就知道-Written in VHDL and the CPU interface for the program, simple and clear, one with the know
Control
- 实现加法器的控制，利用verilog语言。在modelsim环境先实现。-Realization of adder control, the use of Verilog language. In the Modelsim environment to achieve.
led_keyscan
- verilog文件写的微动按键拨码开关检测代码-verilog file micro key DIP switch detection code
lcd12864
- 用FPGA来驱动LCD12864，VHDL语言编写的。-Using FPGA to drive LCD12864，VHDL language
CPLD
- 能够实现DSP的上电复位，并具有硬狗监测，锁存和缓冲的功能。-DSP enables the power-on reset, and having a hard dog monitoring, latching and buffering functions.
latch11
- 自己写的锁存器程序，用VHDL语言实现，望大家指教
test_cpe_top
- fpga开发的程序，内容都不错，主要是top
src
- yuv444 与yuv422相互转换verilog语言-yuv444 to yuv422
FSM
- 序列检测器，采用移位寄存器实现，检测特定序列“101011”-Sequence detector using a shift register implementation, detection of a specific sequence 101011
bvadd
- adder vhdl descr iption