资源列表
PllTwoOrder
- Verilog编写的二阶锁相环代码，环路可以收敛。(Verilog prepared by the second-order phase-locked loop code, the loop can converge.)
dds_synthesizer
- Verilog编写的基于DDS的信号发生器，频率可变。(Verilog prepared by the DDS-based signal generator, the frequency variable.)
adaptive_lms_equalizer
- 自适应算法的verilog实现，是一个很好的学习例子(The adaptive algorithm verilog implementation is a good example of learning)
pipelined_fft_256
- verilog编写的并行256点fft代码(Verilog prepared parallel 256 points fft code)
fadder_4v
- 利用quartus9.0中verilog语言实现的四位全加器，亲测有效(Using quartus9.0 Verilog language to achieve the four bit full adder, pro test effective)
fadder_4
- 利用quartus9.0中元器件模块设计的四位全加器，能运行出结果(Quartus9.0 binary device using the design of four bit full adder, can run the results)
hadder_1
- 用quartus9.0编写的一位全加器，自己设计，能有效运行出结果(Written in quartus9.0 with a full adder, their own design, can effectively run the results)
fadder_1
- 利用quartus9.0编写的半加器程序，自己亲手设计，能有效运行出结果(Quartus9.0 prepared by the semi adder program, personally designed to effectively run the results)
add
- verilog实现的完整的加法器，包括测试文件等(Verilog implements a complete adder, including test files)
modelsim_10.1d破解工具
- modelsim_10.1d破解工具 modelsim_10.1d破解工具(modelsim_10.1d crack tools)
fir
- 基于verilog的 FIR低通滤波器的实现(Implementation of FIR low pass filter based on Verilog)
123
- 3路输入，8路输出的译码器，利用FPGA,BASYS3板子实现该功能，文件已有源代码，仿真代码和约束文件。(3 way input, 8 way output decoder, using FPGA, BASYS3 board to achieve the function, the document already has source code, simulation code and constraint files.)