资源列表
VerilogHDLPLI
- Verilog HDL的PLI子程序接口，用于与用户C程序在2个方向上传输数据，可用xilinx ISE，quartusii或modelsim仿真，-Verilog HDL PLI subroutine interfaces, for C program with the user in the direction of two transmission of data, available xilinx ISE. quartusii or modelsim simulation,
nclight
- 利用硬件描述语言VHDL设计交通灯电路,设计一个十字路口交通灯控制器，东西、南北方向有红灯、黄灯、绿灯，持续时间分别为45、5、40秒。-use VHDL design of traffic lights at the circuit, the design of traffic lights at a crossroads controller East and West, North-South direction of a red light, yellow light, green li
updown-sliding-leds
- updown sliding leds
alm124
- 关于Hspice的仿真实例源码，器件、导线buffer-Example about Hspice simulation,concerning device.wire and buffer
BUS_Control
- fpga上的总线控制器bus_control的控制程序，在数据采集等各个方面都会有很大的用处。-bus controller fpga bus_control control procedures, data acquisition, there will be very useful.
vga controller vhdl de2
- vga vhdl altera de2 for vga screen
h2d
- 使用Verilog语言编写的16进制转10进制程序-Verilog language using hexadecimal decimal program turns 10
LCD1
- lcd controller using vhdl code
keyboard_control
- 用verilog寫得鍵盤控制,可在quatus執行-Verilog is written with the keyboard control, the implementation of the quatus
sinepackage
- SINE package vhdl code
jieshou
- 实现异步串行通信的接受部分，采用vhdl语言实现-Acceptance of asynchronous serial communication part, using vhdl language
BILBO
- A file for Buit In self Test SELF TEST