资源列表
four_bit_addersubtractor
- Verilog code for 4 bit Adder/Subtructor
div
- 对输入时钟clock进行F_DIV倍分频后输出clk_out-Input clock clock for F_DIV times points after clk_out frequency output
tb
- 检测上升沿的verilog程序，有验证程序，可用synplify验证
FirFilter
- 对称型线性相位FIR滤波器的VHDL源程序，比直接型FIR滤波器速度快一半-VHDLSourceProgramofFirFilter
LcdDisp
- 128*64点阵LCD的Verilog代码，LCD为左右半屏各64*64个点，LCDdatasheet可参考ZY12864D.pdf-128* 64 dot matrix LCD, Verilog code, LCD screen is about half of the 64* 64 points, LCDdatasheet refer ZY12864D.pdf
xinjian
- mpsk的解调代码 主要为调制程序的VHDL的仿真程序-mpsk code mainly for the modulation and demodulation process VHDL simulation program
VGA_SYNC
- vga controller in vhdl
part3
- part 3 for verilog -part 3 for verilog aaaa
ssaszhaohengji
- 1．基本要求 （1）频率测量 测量范围:1HZ~1MHZ,信号为方波等 （2）周期测量 测量范围:1HZ~1MHZ,信号为方波等 （3）具有显示功能。 -A. Basic requirements (1) the frequency of measurement Measuring range: 1HZ ~ 1MHZ, the signal is a square wave, etc. (2) The cycle of measurement Measuring ra
uart_tx_and_rx
- A verilog code for UART transmitter and receiver system-A verilog code for UART transmitter and receiver system...
FPGA_Divider
- 本源码是用verilog语言编写的FPGA的除法器和74LS138及D触发器模块。-The source code is written in verilog FPGA divider and 74LS138 and D flip-flop modules.
smj_etester
- 脉宽测试仪FPGA芯片的VHDL核心程序