资源列表
GCD
- synthesis GCD using systemc
C20_sram_vga.rar
- VGA的FPGA试验工程代码。学习vga的可赶紧下！！！！！！！！！！！,VGA demo
FPGA开发全攻略
- FPGA设计攻略及流程，包含时序收敛和引脚约束(FPGA design strategy and process, including time series convergence and pin constraints)
stopwatch
- 基于Verilog的秒表设计，可以在modelsim与开发板环境中正常运行。-A stop watch program based on verilog
SDR-SDRM
- 该工程对三星SDR SDRAM（K4S641632）进行读写，工程内部分为PLL以及复位处理模块、写SDRAM逻辑模块、读SDRAM逻辑模块、SDRAM读写封装模块、读写缓存FIFO模块、串口发生模块等-The project of Samsung SDR SDRAM (K4S641632), read and write, internal engineering points for PLL and reset processing module, SDRAM logic module, S
sdram_mdgray1test
- 使用特权EP1C的开发板，实现数码相框加灰度化功能，用verilog编程。-Privileged EP1C development board to achieve digital photo frame features plus gray, with verilog programming.
ElectronicsVerilog_Digital_Design_Synthesis
- a book which is a guide for verilog beginner
Verilog_Digital_Design_Synthesis
- Verilog HDL A guide to Digital Design and Synthesis Samir Palnitkar SunSoft Press 1996
1904.Verilog-HDL-by-Samir-Palnitkar
- VLSI book for vhdl and verilogg HDL coding
GAL
- 有关gal器件的编程入门，以及常见逻辑门、计数器VHDL程序-For gal device programming entry, as well as common logic gates, counters VHDL program
fpga
- 关于FPGA的相关介绍与一些例程代码实现1(About FPGA related introduction and some routine code implementation)
my_bayer2rgb
- 摄像头Bayer 转rgb信号 用verilog 编写 在xilinx fpga 软件下 ise 综合 编译-Bayer turn the camera rgb signal in xilinx fpga verilog prepared under ise integrated compiler software