资源列表
pipeline_light
- （1）实验1：流水灯实验，完整的设计工程文件在pipeline_light文件夹下-(1) Experiment 1: light water experiments, complete design engineering files in pipeline_light file folder
SystemVerilogAssertions
- Srikanth Vijayaraghavan - A Practical Guide for SystemVerilog Assertions-Srikanth Vijayaraghavan- A Practical Guide for SystemVerilog Assertions
SOPC_NIOS_TEST
- ALTER+NIOS II+SOPC_Builder+NIOS II IDE例程（VHDL）-ALTER+ NIOS II+ SOPC_Builder+ NIOS II IDE routines (VHDL)
FPGA-Advanced-Application
- 一本关于FPGA开发的书籍,是FPGA高级应用的经典著作。其中详细地讲述了整个开发流程,整本书以于xilinx作为硬件平台-A book on the FPGA development, advanced applications of the FPGA classic. Which describes in detail the whole development process, the entire book as the hardware platform in xilinx
LectureNote
- 高级Xilinx FPGA ISE设计教程，详细讲解优化Xilinx设计结构改善时序，减少implementation时间，减少调试时间，片上验证以及调试等FPGA设计深入环节，是深入理解FPGA设计的不可多得的好书。-Advanced Xilinx FPGA ISE design tutorial, explain in detail the structure of the Xilinx design optimization to improve timing, reduce implem
Timing-Analysis
- 关于VHDL/VERILOG进行EDA设计时序分析时需要注意的一些需要注意的问题及处理策略，保证相当实用，请需要的人参考-VHDL/VERILOG the EDA design timing analysis need to pay attention to some issues that need attention and treatment strategies, guaranteed to be quite practical, please need Reference
Codes-and-Reports
- Verilog Source code for arbitrary waveform generator- simple DDS algorithm codes run on Xilinx Spartan-3E fpga to show output on dac pin. Please see the included report. its really simple to implement. all source code is given.
sopc_uart_rt
- sopc的一个应用例程：应用uart部件搭建的一个sopc系统，调试成功了。包含所有源代码-An application of routine sopc: Application uart component erected a sopc system, commissioning a success. Contains all the source code
sp6_BoardTest
- 针对xilinx spartan6芯片做的测试板测试用例-xilinx FPGA product SPARTAN6 test example
test
- sopc 实现板子的灯光的闪烁。验证FPGA的工作性能和可行性。-sopc relize the encoder and decoder of the video .
fpga_qpsk_fsk
- 采用TI的DSP6713协同ALTERA的FPGA芯片实现数字qpsk和FSK调制,并仿真测试成功-TI s DSP6713 collaborative ALTERA FPGA chip digital qpsk and FSK modulation and simulation test was successful.
ahb2wishbone_latest.tar
- AHB总线到wishbone总线的转化的Verilog源码-AHB to wishbone verilog source code