资源列表
quartusii_handbook
- quartusii 的开发手册,方便quartusii学习
22222222222
- 地址线为8位，数据线为八位的正弦信号发生器，采用文本原理图混合输入的方法。-8-bit address lines, data lines for the eight sinusoidal signal generator, using the text input method for mixed schematic.
FPGA
- FPGA开发的相关资料，内容较全，值得学习。-How to develop FPGA.
convolution
- 卷积 严格遵守时序的一维卷积运算，用testbench测试了-convolution write a VHDL file to compute one-dimensional convolution latency 14
ps_bram
- 通过ZYNQ的PS部分读写片上BRAM存储器(Read and write on-chip BRAM memory via the PS portion of the ZYNQ)
429NEW-03-15
- 429总线通过FPGA直接实现发送程序,通过Verilog实现-send 429 message by Verilog and FPGA
start_lab4
- 用Verilog设计一个时间基准电路和带使能的多周期计数器，并在此基础是设计一个简单的秒表0.0-10.0计数- Verilog design with a time reference circuit and with enable multi-cycle counter, and on this basis is to design a simple stopwatch count 0.0-10.0
Altera-FPGA_CPLD-design-Advanced
- 《Altera FPGA_CPLD设计 高级篇》详细介绍FPGA应用于高级特性，LogicLock设计，时序约束，设计优化，高级工具及系统级设计技术，是深入学习FPGA的重要材料-" Altera FPGA_CPLD advanced part design" details FPGA used in advanced features, LogicLock design, timing constraints, design optimization, system-leve
AlteraPFPGA_CPLD
- FPGA和CPLD的学习资料，从初级到高级，从基础到深入，对于学习FPGA的初学者很有用处。-FPGA and CPLD learning materials, from beginner to advanced, from basic to in-depth for beginners learning FPGA useful.
AlteraFPGA_CPLD
- Altera FPGA_CPLD设计 高级篇[1]\Altera FPGA_CPLD设计 高级篇.pdf-Altera FPGA_CPLD design advanced part [1] \ Altera FPGA_CPLD advanced part design. Pdf
dvb_s2_ldpc_decoder_latest.tar
- DVB LDPC编码 文档资料完整，值得收藏的DVB编码-DVB LDPC coded documentation is complete, it is a collection of DVB encoding
dvb_s2_ldpc_decoder_latest.tar
- 用于数字电视机顶盒的DVB-S2的LDPC编码的解码模块，verilog代码-For digital TV set-top boxes of DVB- S2 LDPC coding, decoding module of verilog code