资源列表
EDAteaching
- 系统介绍EDA技术的发展概述，相关概念，VHDL语言、MAX+PULS、QUARTUS的设计方法。-System overview of the development of EDA technology, related concepts, VHDL language, MAX+ PULS, QUARTUS design method.
NIOS_TFT
- 用Quartus II 8.0（32bit），NIOS编译环境下，用TFT做的一个数码相框，附加原理图和veri-log程序代码-Using Quartus II 8.0 (32bit), NIOS compiler environment, TFT do with a digital photo frame, attached schematic and program code veri-log
ece5760-final-cwf38-mao65-as889
- BALL GAME + EDGE DETECTION FOR FPGA
AN152
- AMBA Application Note: AN152 - Using EB with CT11MPCore Core Tile. -This example shows how to use the EB baseboard with a CT11MPCore Core Tile. AMBA Application Note: AN152- Using EB with CT11MPCore Core Tile. The following board combinat
nova
- 基于H.264 视频编解码 verilog 基于H.264 视频编解码 verilog-Verilog based on the H.264 video codec based on H.264 video codec Verilog
my_eda(3-7)
- 一些关于VHDL的基础小模块程序，比如分频，计数，移位，锁存等程序-Some small modules based on the VHDL program, such as frequency, counting, shift, latches and other procedures
tcp_tiaoshi
- fpga_sopc_enc28j60_tcp_ip_测试，源码程序包，本人测试通过！-Fpga_sopc_enc28j60_tcp_ip_ test, the source code packets, I test through!
IMAGE_0424
- FPGA实现视频图像实时缩放功能 QUARTUS环境下测试成功-FPGA to achieve real-time video image zoom feature
1-wireDS18B20
- 基于Nios II设计的1-wire数字温度计-Nios II-based design of digital thermometers
LVDS_Serdes_list_FPGA1
- FPGA之间的LVDS传输，采用serdes接口，传输速率达到400m-LVDS transmission between the FPGA using serdes interface, transfer rate up to 400m
VerilogDesignand-test_PdfPCode
- Verilog 设计与验证源码+PDF，经典教程，对与RTL和状态机的理解有很大帮助，适合FPGA开发工程师。-Verilog design and verification source+ PDF, classic tutorial, and state machine understanding of RTL helps a lot, suitable for the FPGA development engineers.
13.3_Tracing
- 基于System Generator的图像处理工程,多媒体处理FPGA实现的源码,基于视频的运动跟踪-System Generator based image processing engineering, multimedia processing on FPGA source, video-based motion tracking