资源列表
MD5Transform
- 本人设计的一个基于FPGA平台用verilogHDL设计的MD5加密，供FPGA学习者学习参考-a MD5 encoder designed by me.It s a learning code for FPGA learner
FPGA_DDS
- 基于FPGA的DDS信号发生器产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-FPGA-based VHDL source DDS signal generator and the test stimulus file matlab model simulation in modelsim adopted under
ucos_niosii
- 在FPGA硬件体系下，搭建软核处理器NIOSII，进而用NIOSII运行ucos操作系统，从硬件到软件完全实现用户定制-In the FPGA hardware system, the structures of soft-core processor NIOSII, and then run with NIOSII ucos operating system, from hardware to software to fully implement custom
radio_na_TEA5767
- It contains the source code files use the module on the radio TEA5767 I2C written in AVR Studio 4 for Atmega8. It also includes circuit diagram and documentation.
CORDIC_SINE
- xilinx的ISE工程，用CORDIC算法做DDS生成正弦波-xilinx the ISE project to do with the CORDIC algorithm generates sine DDS
EPM240
- 开发板配套教程里的很多个实验 方便从初学开始 含有VHDL和verilog HDL语言-Development board supporting the many tutorial easy experiments start from the beginner with the language VHDL and verilog HDL
fftshixian
- 基于FPGA编写的verilog代码，在xilinx上仿真实现FFT变换-FPGA-based verilog code written in xilinx FFT transform Simulation
mig007
- XILINX memory interface generator. XILINX的外部存储器接口。-XILINX memory interface generator.
VHDL_code
- 基于FPGA的AD,DA,LCD,LED,CAN,I2C,PS2,VGA以及一些通讯ASK,FSK等的VHDL源程序，所有程序已通过调试，需要的拿走。-FPGA-based AD, DA, LCD, LED, CAN, I2C, PS2, VGA, and some communications ASK, FSK, etc. VHDL source code, all procedures have been debugging, need to take.
8051
- 在EP2C5上进行8051单片机的核移植-8051 on the EP2C5 nuclear transplantation
spi_no_cs_13
- FPGA作为从机与STM32的全双工通信，FPGA将接收到STM32的数据返回到STM32，Modelsim仿真和板子仿真都通过(Use FPGA as slave,realize the communication between FPGA and STM32. The function has been tested is no problem.)
Dec_mul
- 时间同步后即可确定每帧数据的起始位置，这样就能完整的截取下每一帧。但是，数据中还带有频偏信息。在常规的通信系统中，多普勒很小仅仅会带来很小的频偏，但是在大多普勒的情况下，频偏将非常大，20马赫的速度将会带来将近34K的频偏。因此，如何很好的纠正频偏即为本系统的难点。 OFDM中，我们将大于子载波间隔倍数的频偏称为整数倍频偏，而将小于一个子载波间隔的频偏称为小数倍频偏。频偏矫正精度只要能保证小于十分之一倍的子载波间隔，频偏就不会对均衡和解调造成影响。本文中我们借鉴这种思想，由于硬件资源限制，我