资源列表
low_cost_lcd
- niosII基础上实现的嵌入式网络驱动，niosII基础上实现的嵌入式网络驱动-niosII based on the embedded network drive, niosII based on the embedded network drive
nios2_ucos2
- 基于Altera的FPGA配置的Nios2软核，移植了uC/OS2操作系统。实现的功能包括1602字符液晶驱动，基于中断的4*4矩阵键盘检测，流水灯。所有C文件位于\software\nios2_hello_ucosii目录下。 -Embedded Nios2 System based on Altera s FPGA, with uC/OS2 RTOS transplanted. Function included: 1602 character LCD display, 4*4 matr
ADSample3
- 这是我自己做的项目中的FPGA程序，和之前的是一个项目中一个-This is my own project FPGA program, and before a project
EDA
- FPGA的EDA实验，里面有详细的PDF说明-FPGA EDA experiment, which has a detailed descr iption of the PDF
Quartus2(FPGACPLD)
- 在Quartus2上的FPGACPLD设计，PDF文档-The FPGACPLD design in Quartus2 , PDF documents
svpwm_full_nios
- 实现verilog的svpwm 对于算法开发有很好的帮助。。希望大家多多学习了。(Implementation of verilog svpwm for the development of the algorithm has a very good help. The I hope you learn a lot.)
CORDIC_testt
- cordic旋转以及testbench，可以作为givens旋转的一个单元使用，有很强的工程价值-cordic and testbench
VLSI-Project-Median-filer
- FPGA和ASIC实现的图像中值滤波模块，各模块的仿真结果以及MATLAB,Modelsim联合仿真。这是中科大超大规模集成电路设计优化的final project。附有最终版的report和presention。-FPGA and ASIC implementation of image filtering modules, each module of the simulation results and MATLAB, Modelsim co-simulation. This is the
shuzi1216
- vhdl 语言入门-VHDL language portal
time
- FPGA做的电子钟，通过定时器实现。用vhdl做的led ip核，软件实现控制显示-FPGA do electronic bell, by timer implementation. Led ip vhdl do with nuclear, software control display
矩阵计算
- 用于矩阵计算的Verilog源代码，实测可用，欢迎下载。
8051_test
- 8051_test 在nios中嵌入单片机51核-8051_test embedded microcontroller 51 in the nios core