资源列表
22_xiaodou
- 基于FPGA功能实现按键消除抖动，xiaodou里面有已经好的程序，可直接下载使用(Key elimination jitter based on FPGA function implementation)
VerilogHDL硬件描述语言
- Verilog语言入门教程，详细讲述了Verilog语法和应用(Verilog language introductory course, detailing the Verilog syntax and Application)
8_uart_test
- 串口通信，基于Quartus的用Verilog实现串口通信(Serial communication and serial communication with Verilog based on Quartus)
6_key_test
- 键盘按键，基于Quartus的用Verilog实现键盘扫描(The keys on the keyboard, Quartus keyboard scanning based on Verilog implementation)
FRJ_HN1702_Assignment3_ThangNN6
- Horizontal size of Unix machines. The latest name of the AS400 is the IBM Iseries (I = Integrated), which is integrated because it is sold with all the pre-installed programs. The AS400 is aimed at mid-market companies, with few technical teams to ma
CIC_Filter_Module
- 数字接收机cic抽取模块 抽取倍数可以选择 包括verilog代码 word文档 matlab仿真 testbench代码(CIC decimation module of digital receiver Extraction multiple can be selected Including Verilog code Word document Matlab simulation Testbench code)
Orthogonization_Module
- 接收机数字部分正交混频模块‘ 包括verilog代码 matlab仿真 word文档 testbench代码(Receiver digital part orthogonal frequency mixing module ' Including Verilog code Matlab simulation Testbench code)
FFT_Module
- 接收机数字部分FFT模块的代码 包括verilog代码、 matlab仿真、 word文档 testbench 实现FFT(The code of the digital part FFT module of the receiver Including Verilog, matlab simulation, testbench Implementation of FFT)
Clock_Synchronization_Module
- 数字接收机中频部分数字时钟的设计 包括matlab仿真 verilog代码、 testbench代码 以及word设计文档(Design of medium frequency digital clock in digital receiver Including Matlab simulation Verilog, testbench code, and design documents)
ADC_Data_Recv_Module
- 接收机测试输入信号， 生成正余弦波，采样率、频率、幅度、相位可调节 并将生成的数据进行输出 压缩包包括Verilog代码、testbench代码、word文档 matlab仿真代码(The receiver tests the input signal, Generation of positive cosine wave, sampling rate, frequency, amplitude, phase can be adjusted And output the generated da
elevator
- 电梯运行的控制系统，FPGA实现，基于Verilog(Control system of elevator operation)
Xilinx的增量编译技术
- 增量编译技术，其基本原理就是根据前一次编译的结果，只重新编译部分修改过设计，其它部分则沿用前一次编译的结果，这样就可以缩短总体的编译时间(Incremental compilation technology, the basic principle is based on the results of the previous compilation, only re-editing part of the modified design, the other part is based on