资源列表
VHDL1
- VHDL语言教程，初级的编程语言以及语法，适合初学者-VHDL language tutorial, the primary programming language and grammar, suitable for beginners
TLC5620
- 用FPGA做的8位DAC的驱动，数据通过串口发送，测试精度一般。-Drive the use of FPGA in the 8 bit DAC, via a serial port to send data, test precision.
[verilog]dcfifo_256x32
- Dual-Clock FIFO, Depth: 256 Width: 32 USEDW: Y FULLL:Y EMPTY:Y-This is self-defined Dual-Clock FIFO, using logic lut resources.
Q_GDW_MS
- 实现了国家电网智能家居通信协议标准的智能开关的功能-To achieve the national grid smart home communication protocol standard intelligent switch function
dds
- 用VHDL语言实现的dds信号的源代码，已测验，可通过-dds in vhdl
FUZZY
- verilog 模糊PID 通过修改MIF文件 可以完成单个参数整定-FUZZY pid by verilog HDL
FPGA-program-for-sapce-application
- 航天应用的FPGA程序的典型案例分析，含源代码；特别适合于航天领域的FPGA程序设计员。-typical examples of fpga programs for space application
seg7
- 数码管实验，包括段选位选，通过了FPGA开发板验证。-Digital tube experiments, including the election of the selected segment, through the FPGA development board validation.
johnson
- 流水灯程序，可以满足JTAG和AS两种配置方式，已验证-Water light program, you can meet the JTAG and AS two configurations, has been verified
UART_noFIFO
- FPGA串口调试程序，不含FIFOIP核-FPGA u4E32 u53E3 u8C03 u8BD5 u7A0B u5E8F uFF0C u4E0D u542BFIFOIP u6838
xianshi
- 用汉字点阵码编10个字的短句（可以是专业介绍、古诗片段），移动显示，分帘请屏、正常及镂空显示-Chinese character dot matrix code compiled 10 words of the phrase (can be a professional introduction, ancient poetry fragments), mobile display, sub screen, screen, normal and hollow display
exp2_fpga
- Arithmetic logic unit