资源列表
EDA
- 熟悉QuartusⅡ的Verilog HDL文本设计流程全过程，学习计数器的设计、仿真和硬件测试。-Familiar with Quartus II Verilog HDL text design process, learning counter design, simulation and hardware testing.
DDS
- 四通道DDS信号发生器,Four channel DDS signal generator-Four channel DDS signal generator
DDS_BPSK
- 基于DDS的BPSK调制器设计Verilog源码- U57FA u4E8.08 u868
_MATLAB_AND_FPGA_AlteraVerilog
- 数字通信同步技术的MATLAB与FPGA实现 Altera/Verilog版- U6570 u5B57 u901A u4FE1 u540C u6B65 u6280 u672F u7684MATLAB u4E0EFPGA u5B9E u73B0 Altera/Verilog u7248
simple
- FIRST WORD FALL THROUGH FIFO
arm4u_latest.tar
- DESIGN OF A DYNAMICALLY RECONFIGURABLE PIPELINED RISC PROCESSOR
ps2verilog
- PS2键盘解码源程序，亲测可用，希望对大家有帮助-PS2 keyboard decoding source, pro-test available, we hope to help
pc_fpga_com_latest.tar
- 用VHDL实现的PC与FPGA之间的网络通信，通过以太网进行通信-comunicate between PC and FPGA via ethernet
DDS
- 利用ISE中的ip核产生正弦和余弦波形，包含有test测试文件-ISE ip core cosine sine testbench
verilogiic1121
- I2C通信源代码，调试完可以使用，希望对大家有帮助-I2C communication source code, debugging can be used, we hope to help
firfilterPfpga
- FIR滤波器的仿真，使用ISE软件verilog语言。其中滤波器系数为matlab产生的.coe文件，并产生testbench文件进行仿真。-FIR filter verilog coe testbench
square_root_n_bits
- VHDL square root - compute square root n (n customizable) bits width vector (restoring square root algorithm)