资源列表
Steppermotor-VHDL
- Stepper motor positioning control system VHDL program and simulation
dfe_filter
- DEF算法的FIR滤波器verilog代码，内有乘法器IP核，可直接仿真使用-DEF algorithm for FIR filter verilog code with multiplier IP core, can be directly used simulation
interpolate4
- 调制信号后4倍内插的verilog代码，用于基带成型滤波器输入数据-4 times after modulation signal interpolation verilog code, used to baseband shaping filter input data
FIR_lowpass
- 一个FIR低通滤波器的fpga源码，可以应用于通信调制成型滤波器参考代码-A FIR low-pass filter in the fpga source code, can be used in the communication reference code modulation shaping filter
sdram_ov7670_vga
- 基于FPGA的CMOS摄像头视频采集传输，lcd显示。-FPGA-based CMOS camera video capture transmission, lcd display.
CommunicationICdesign
- 通信IC设计的附件里面是通信IC设计这本书各章节的源代码非常详细有利于fpga通信开发-Communication IC design of the annex which is the communication IC design The chapters of the book are very detailed in the source code is conducive to fpga communication development
pingpang_ram
- 乒乓RAM静态随机存储器的控制，用于解决数据流连续存储问题。-Ping pong RAM static random access control, to solve the problem of continuous data flow storage.
show1234in01
- 基于quartus软件上的多位数码管，可用于显示1234.-Based on the number of digital quartus software can be used to display 1234.
fft4_T
- 4点FFT处理器设计，流水线式结构。采用状态机，不停地循环。-4-point FFT processor design, pipelined structure. Using the state machine, keep the cycle.
Bin2BCD
- FPGA代码，使用Verilog HDL语言实现4 bit二进制转换成BCD代码。原理是移位加三。-FPGA code, using Verilog HDL language is converted into a binary 4 bit BCD code. The principle is Shift-Add-3 .
Multiplier
- 复用全加器来实现乘法器, 通过从右到左互为输入输出，实现低位计算。最左向高位输出。具体要求请参见附带的PDF。-Multiplexing a multiplier to achieve full adder, input and output by each other right to left, the least significant bits is calculated. Most left output to high. Specific requirements Refer to
Verilog-fmq
- FPGA驱动蜂鸣器，Verilog语言，蜂鸣器奏乐-FPGA driver buzzer, Verilog language, buzzer music