资源列表
optisystem7.0P()
- optisystem7.0组件库的翻译文件 较为详实-Optisystem7.0 component library translation file is more detailed
HDB3
- 针对数字基带传输系统中HDB3信号的特点，采用基于FPGA的Verilog HDL语言，实现HDB3数字基带信号的编码器设计,共有插V、插B、单双极性变换模块，最终能在FPGA实现。-For digital baseband transmission system HDB3 signal characteristics, based on FPGA Verilog HDL language, designed to achieve HDB3 encoder digital baseband si
5_Gray_Mean_Filter
- 均值滤波是典型的线性滤波算法，（Verilog HDL）设计所需的模块有： （1）带PLL的全局时钟管理模块 system_ctrl_pll.v （2）OV7725 COMS Sensor的初始化模块 i2c_timing_ctrl、I2C_OV7725_RGB565_Conofig （3）OV7725 COMS Sensor的视频信号采集模块COMS_Capture_RGB565 （4）SDRAM数据交互控制器Sdram_Control_2Port （5）VGA时序
3_FirFullSerial
- 基于Quartus II 13.0的FirFullSerial工程设计基本流程，内含详细doc文档-Based on Quartus II 13.0 FirFullSerial basic engineering design process, it contains a detailed doc document
2_Mixer
- 基于Quartus II 13.0 的将两信号进行混合相乘的源码，适合于新人熟悉掌握该软件使用-Based on the Quartus II 13.0 mix two signal multiplication of the source code, suitable for a new master to use the software
2_CMOS_OV7725_Gray_Sobel
- 基于Quartus II 的灰度边缘检测源码，从输入端获取信息，可输出灰度边缘化图像，需要一定设备-Gray edge detection based on Quartus II source, obtaining information the input end, images can be output gray scale marginalized, need certain equipment
Phase_collect04
- 用于FPGA控制传感器采集程序并进行存储.通过RAM进行存储。-FPGA control program for collecting and storing the sensor. Stored by the RAM.
PLL_PID
- 以PID控制实现的Phase detector_Loop Filter_VCO-Phase Locked Loop
tlc549uart
- 利用EP2C8Q208C8N芯片控制串口通信，FPGA,Verilog-Using EP2C8Q208C8N chip control serial communication, FPGA, Verilog
m_xulie
- m序列发生器，并进行曼彻斯特编码,亲自编写，已经经过验证-m-sequence generator, and Manchester encoding
FPGA
- EP3C16F484-datasheet以及EP3C16F484开发板的电路图-EP3C16F484-datasheet and EP3C16F484 development board circuit diagram
intro_to_quartus2_chinese
- ALTER公司的官方版Quartus® II 简介，包括基本的设计流程，布线等 -ALTER s official version of the Quartus® II profile, including the basic design process, wiring and so on