资源列表
8位可预置的循环移位数字信号发生器、简易逻辑分析仪
- 简易逻辑分析仪的设计用源代码,为05年电子大赛2等奖作品-simple logic analyzer with the design of the source code for electronic 05 2 Prize Competition works
Synthesisofverilog
- 一篇有用的Verilog语言综合问题研究-a useful comprehensive Verilog language study
odd_divider_VHDL
- 常用1、3、5及任意奇数分频器的VHDL代码实现（原创）-used 1,3,5 and arbitrary odd Divider VHDL code to achieve (original)
even_divider_VHDL
- 常用2、4、6及任意偶数分频器的VHDL代码实现（原创）-used 2,4,6 and even arbitrary divider VHDL code to achieve (original)
PulseWidth_detector_VHDL
- 通信控制中常用的脉冲宽度检测程序，VHDL模块化编成实现（原创）-communication control used in pulse width detection procedures, VHDL modular organization to achieve (original)
N_counter_VHDL
- 任意N进制分频器的标准VHDL代码（原创）-arbitrary N divider 229 standard VHDL code (original)
ModelSim_TestBench_VHDL
- ModelSim TestBench的VHDL模版-ModelSim VHDL template TestBench
deinterlace
- Xilinx提供的一种利用线缓存进行插值的隔行变逐行程序，比普通算法效果有很大改进。-Xilinx to provide a linear interpolation for the cache interlaced progressive change procedures, than ordinary algorithm results are greatly improved.
ycrcb_rgb
- YUV转RGB的源程序，使用到了硬件加速器，可利用FGPA的乘法器加速处理速度。-YUV to RGB source, the use of a hardware accelerator, FGPA can be used to speed up the processing speed multiplier.
lf_decode
- 检测BT.656视频格式中内含的同步信号，可分离出行场同步信号。-detection R BT.656 video format containing the synchronization signal separable travel market synchronous signal.
KPCSMII
- Xillinx 的8位MCU软核的源代码，可在VertexII上运行，对CPU设计人员有很大参考意义-Xillinx the eight MCU soft-core source code can be run in VertexII. CPU designers to have great reference value
422_to_444
- YUV422转YUV444的FPGA插植算法，由Xilinx提供-YUV422 to YUV444 FPGA implantation algorithm provided by Xilinx