资源列表
sdram_verilog
- 这是使用VERILOG语言，基于MICRON公司的SDRAM开发的SDRAM接口逻辑-verilog This is the use of language, MICRON-based company's development of the SDRAM SDRAM interface logic
simple_cpu
- 初学cpu结构的很好的verilog代码的示例，适合初学者-novice cpu structure of the good verilog code examples for beginners
DigitalClockVHDL
- 多功能电子时钟的VHDL源代码。使用MAX+PLUS II进行编译。该文档有详细的说明和程序注释。-VHDL source code. Use MAX PLUS II computer. The document is described in detail in the Notes and procedures.
VHDL-status
- VHDL状态机学习笔记,对初学者有很重要的帮助意义-VHDL state machine learning notes for beginners has a very important significance help
Verilogmanual
- VERILOG语言速查手册,与VHDL齐名的另外一硬件描述语言-verilog language manuals, and the other enjoying VHDL hardware descr iption language 1
three-vhdl
- VHDL下实现3分频率波形,完整源代码,学习参考-VHDL under three frequency waveform, complete source code, study reference
ndivider
- VHDL源代码实现任意个分频,值得推荐学习-VHDL source code to achieve arbitrary sub-frequency, it is worth learning recommended
shockware
- VHDL 波形防止抖动程序,学习试验材料-VHDL prevent jitter waveform procedures, the pilot study materials
s_machine
- right.vhd 序列发生器 s_machine.vhd 序列检测器 波形图.doc 程序运行波形-right.vhd s_machine.vhd sequence generator waveform sequence detector map. doc procedures Waveform
seven
- seven.vhd 七人表决器VHDL源码 七人表决器.doc 程序说明-seven.vhd seven votes for VHDL source code for seven votes. A descr iption of the procedures for doc
count16
- count16.vhd 16位BCD计数器VHDL源程序-count16.vhd 16 BCD counter VHDL source
multi4
- fulladder.vhd 一位全加器 adder.vhd 四位全加器 multi4.vhd 四位并行乘法器-fulladder.vhd a full adder adder.vhd four full adder mult i4.vhd four parallel multiplier