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  1. Shifters_vhdl

    0下载:
  2. -- Title : Barrel Shifter (Pure combinational) -- This VHDL design file is an open design you can redistribute it and/or -- modify it and/or implement it after contacting the author -- You can check the draft license at --- Title : Barrel Shift
  3. 所属分类:VHDL编程

    • 发布日期:2008-10-13
    • 文件大小:1.98kb
    • 提供者:陈朋
  1. DCT_vhdl

    1下载:
  2. IDCT-M is a medium speed 1D IDCT core -- it can accept a continous stream of 12-bit input words at a rate of -- 1 bit/ck cycle, operating at 50MHz speed, it can process MP@ML MPEG video -- the core is 100% synthesizable-IDCT-M is a medium speed
  3. 所属分类:VHDL编程

    • 发布日期:2008-10-13
    • 文件大小:10.48kb
    • 提供者:陈朋
  1. DaFilter

    0下载:
  2. /* This program generates the DApkg.vhd file that is used to define * the DA filter core and gives its parameters and the contents of the * Distributed Arithmetic Look-up-table \"DALUT\" according to the DA algorithm-/ * This program generate
  3. 所属分类:VHDL编程

    • 发布日期:2008-10-13
    • 文件大小:15.23kb
    • 提供者:陈朋
  1. binary2bcd

    0下载:
  2. This build is for developing a \"binary-to-BCD\" converter for use in // displaying numerals in base-10 so that people can read and interpret the // numbers more readily than they could if the numbers were displayed in // binary or hexadecimal
  3. 所属分类:VHDL编程

    • 发布日期:2008-10-13
    • 文件大小:41.46kb
    • 提供者:陈朋
  1. lpm_mul

    0下载:
  2. 8*8的乘法器verilog源代码,经过编译仿真的,绝对真确,对初学者很有帮助-8 * 8 Multiplier verilog source code, compiled simulation, absolute authenticity, helpful for beginners
  3. 所属分类:VHDL编程

    • 发布日期:2008-10-13
    • 文件大小:27.15kb
    • 提供者:刘东辉
  1. yimazhenque

    0下载:
  2. 47译码器器的verilog源代码,经过编译仿真的,绝对真确,对初学者很有帮助-47 decoder for verilog source code, compiled simulation, absolute authenticity, helpful for beginners
  3. 所属分类:VHDL编程

    • 发布日期:2008-10-13
    • 文件大小:21kb
    • 提供者:刘东辉
  1. xapp616

    1下载:
  2. A Huffman implementation reference design in both VHDL and Verilog is provided by the Xilinx-A. Huffman implementation reference desig n in both VHDL and Verilog is provided by the Xili nx
  3. 所属分类:VHDL编程

    • 发布日期:2008-10-13
    • 文件大小:13.14kb
    • 提供者:窦洪山
  1. Avalon_VGA

    0下载:
  2. Avalon_VGA,-- This design provides an interface to the Alcahest VGA daughter card. -- The design comprises of an 8-bit VGA driver with Avalon bus interfaces. There are a total of -- three Avalon interfaces.-Avalon_VGA. -- This design provides an
  3. 所属分类:VHDL编程

    • 发布日期:2008-10-13
    • 文件大小:15.99kb
    • 提供者:陈朋
  1. EthernetMAC10100Mbps.tar

    0下载:
  2. ethernet 10 0M MAC-ethernet MAC 10,100 M
  3. 所属分类:VHDL编程

    • 发布日期:2008-10-13
    • 文件大小:912.91kb
    • 提供者:wing
  1. seq_gen_576

    1下载:
  2. 高清电视HDTV信号发生器,576P逐行,VHDL语言,ALTERA的Quartus II开发平台-HDTV HDTV signal generator, 576P progressive, VHDL, Altera's Quartus II development platform
  3. 所属分类:VHDL编程

    • 发布日期:2008-10-13
    • 文件大小:158.34kb
    • 提供者:lidan
  1. 1553_enc_dec

    1下载:
  2. 1553B的编解码程序很好用给大家分享 -the series 1553B decoder procedure is useful for everyone to share share
  3. 所属分类:VHDL编程

    • 发布日期:2008-10-13
    • 文件大小:31.2kb
    • 提供者:黄名
  1. CummingsSNUG2002SJ_Resets

    0下载:
  2. Synchronous Resets? Asynchronous Resets?I am so confused!How will I ever know which to use? 复位信号的论文-Synchronous Resets Asynchronous Resets I am so confused! How will I ever know which to use Minute Signal-paper
  3. 所属分类:VHDL编程

    • 发布日期:2008-10-13
    • 文件大小:237.35kb
    • 提供者:黄名
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