资源列表
Div20PLL
- 使用VHDL实现锁相环,是个学习VHDL的好例子,与众分享-PLL using VHDL, VHDL is learning a good example, sharing with the public
n2cpu_nii5v3_01
- 这是介绍嵌入式开发相关的资料。有总线与内存的操作-introduced Embedded Development relevant information. Bus and a memory operation
200691151948398
- 这是一个也介绍GPIB编程的文章以及介绍GPIB协议规范-This is a GPIB programming also introduced the article and introduce GPIB norm
LDOTESTSYSTEM
- 这是一个GPIB源程序代码,里面有硬件相对应的代码-This is a GPIB source code, which corresponds to a hardware code
produce
- vhdl的一个串行序列信号发生器的设计与实现-vhdl sequence of a Serial Signal Generator Design and Implementation
SystemVerilog_FIFO_Channel
- 2004 SNUG of systemverilog
adma
- Wishbone dma ip core
S3Demo
- 用FPGA模拟VGA时序、模拟PS/2总线的键盘接口VHDL源代码，基于Xilinx spartan3-VGA FPGA timing simulation, simulation PS / 2 keyboard interface bus VHDL source code, Based on Xilinx spartan3
xcv
- verilog编写的状态机检测00100序列. 实现 input:...011000010010000... output:...000000000100100... 并且 用测试模块来验证状态是否正确工作-verilog prepared by the state machine detected 00,100 sequences. Achieve input : ... ... 011000010010000 output : 000000000100100 ... ... a
CALCULAT.ZIP
- verilog源码，可实现两位的加法器，在xillinx foundation 3.1下验证通过-verilog source, the two can achieve Adder, In xillinx foundation 3.1 certification through
veriexamples
- 非常多的verilog实例，对于刚入门者比较有用-lot of verilog example, just beginners more useful
Lab20
- the booth algorithm to implement the 32bits multiplication.-the booth algorithm to implement the 32bit 's multiplication.