资源列表
Parall_transfer_seior
- 此两文件是在MAXplusII环境下开发并运行通过的VHDL文件，实现了并串口转换功能。-this document is in two MAXplusII environment through the development and operation of the VHDL documents, and the realization of serial conversion function.
S2P_xapp194
- VHDL，verilog串并转换源程序 Xilinx公司参考资料-VHDL, verilog Series and conversion company Xilinx reference source
LCD_fullscreen
- 这是本人写的可显示128*64LCD全屏汉字的程序,直接下到片子里即可出现象(需自己定制ROM).想显示第二屏的话只需加一个状态即可.-I write this is the display of 128 * Embedded full screen characters procedures, directly to the unit under the blankets will be out phenomenon (it-yourself customized ROM). to the s
usb1.1phy
- USB 1.1 PHY的代码，verilog语言 USB 1.1 PHY的代码，verilog语言-USB 1.1 PHY code, verilog language USB 1.1 PHY code, verilog language
count_top
- VGA计数，PSW2控制正逆计数，按下递减计数，弹起正向计数。利用VGA作为输出设备，显示计数值。-VGA count, PSW2 inverse control is counting? Reduced count, pop-up being counted. The use of VGA as the output equipment, revealed count.
20060510205455473
- vhdl设计事例,有助于FPGA初学着,High-Performance 1024-Point Complex FFT-vhdl design examples, to help novice FPGA. High-Performance 1024-Point Complex FFT
wave_gen
- 波形发生器，带TESTBENCH， 多平台 -- the design makes use of the new shift operators available in the VHDL-93 std -- this design passes the Synplify synthesis check -- download from: www.fpga.com.cn & www.pld.com.cn -waveform generator, with TESTBENCH.
BoothMultiplier
- -- Booth Multiplier -- This file contains all the entity-architectures for a complete -- k-bit x k-bit Booth multiplier. -- the design makes use of the new shift operators available in the VHDL-93 std -- this design passes the Synplify synthe
FSM02
- 异步复位状态机 -- State Machine with Asynchronous Reset -- dowload from: www.fpga.com.cn & www.pld.com.cn -asynchronous reset state machine -- State Machine with Asynchronou 's Reset -- dowload from : www.fpga.com.cn
mo0re_FSM
- -- Moore State Machine with explicit state encoding -- dowload from: www.fpga.com.cn & www.pld.com.cn--- Moore State Machine with explicit state encoding -- dowload from : www.fpga.com.cn
decode_for_m68008
- -- M68008 Address Decoder -- Address decoder for the m68008 -- asbar must be 0 to enable any output -- csbar(0) : X\"00000\" to X\"01FFF\" -- csbar(1) : X\"40000\" to X\"43FFF\" -- csbar(2) : X\"08000\" to X\"0AFFF\" -- csbar(3) : X\"E000
fifo_01
- 8位相等比较器，比较8位数是否相等 -- 8-bit Identity Comparator -- uses 1993 std VHDL -- download from www.pld.com.cn & www.fpga.com.cn-eight other phase comparators, Comparing the same whether the median 8 -- 8-bit Identity Comparator -- uses 1993 std VHDL --