资源列表
mj10
- 实现门禁系统，可以做网店实战的项目，对接数据库，不过里面没有数据库想对应的测试数据(The implementation of the entrance guard system, can do online shop actual projects, docking database, but there is no database to corresponding test data in it.)
and_gate
- ALU设计与开发，四位的，简单可仿真，内部里面有text班车(ALU design and development, four bit, simple and emulation)
spi_8r8w
- 同时实现多个SPI从设备的连续读写，读写字节数可变化(implement multiply spi slave read/write operation, and the operation's bytes can be changed)
Single_cpu
- 单周期CPU自己课程大作业做的，亲测好用，verilog语言，适用vivado(Single cycle CPU course to do, pro - use, Verilog language, suitable for vivado)
Multi_cpu
- 多周期CPU自己课程大作业做的，亲测好用，verilog语言，适用vivado(Single cycle CPU course to do, pro - use, Verilog language, suitable for vivado)
Up_Down_Counter v1.0
- FPGA Up/Down couner Module
RGMII_RECEIVER
- This module converts 4 bit DDR RGMII flow to 8 bit SDR flow, proved on Altera Cyclone 3 devices.
循环码
- 这是对于循环码编码器的语言，希望对大家有帮助(This is the source code for cyclic code coding, I hope to help everyone)
shuzhizhong (1)
- 数字时钟的FPGA设计，对学习FPGA有很大的帮助，希望大家能采纳(FPGA design of digital clock has great help for learning FPGA. I hope everyone can adopt it.)
FSM two sequence
- FSM sequence detector
2_FFs
- Flipflop with all possible combination verilog
rom_test
- rom读写实验，实现FPGA内部rom数据存取(rom read and write,this is a good document for study FPGA verilog)