资源列表
UP3_CLOCK
- 用vhdl编写的时钟 主要实现了时钟功能时间调教功能有待实现 -prepared using VHDL clock main function of clock time tuning function to be achieved
JPEG2000_FPGA_Design
- 本论文主要论述JPEG2000中嵌入式块编码的FPGA设计，非常有参考价值-this paper mainly discusses JPEG2000 coding embedded blocks of FPGA design, a very valuable reference
ethern
- 此代码是用Verilog实现的以太网接口,在此基础上做修改,可以作为一般的以太网接口程序开发.-this Verilog code is used to achieve the Ethernet interface, in this done on the basis of changes as a general Ethernet interface development.
cla_vhd
- 超前进位加法器的例子,包括源码和测试文件,压缩包,无密码.-CLA of examples, including source code and test documents, compressed, without a password.
ARM9_instruction_cache_verilogCodes
- Arm9指令Cache缓存模块的verilog代码，对一些做ARM硬件开发的朋友有参考价值。-Arm9 Instruction Cache Cache Module Verilog code, do some of the hardware development of the ARM friends reference value.
wavegenerator_testbench
- 此文件采用了verilog语言在cpld中怎样实现波形发生器，及其验证程序-this document using the Verilog language in the cpld How to achieve waveform generator, and the verification process
digitalinterfaceuart
- 文件说明了在fpga/cpld中怎样实现数据接口及其实例了urat-note of the document they simply / cpld How Data Interface and the examples of urat
plldigitalclock
- 此文件是FPGA中数字时钟开发，包括时钟的分拼 ，备品-file is a digital clock FPGA development, including the sub-clock fight, spare
sericommu
- 串口通信程序.在波特率为9600的串口通信程序-serial communication program. The baud rate for the 9600 serial communication program
1.i2c_slave
- I2C的slave端程序,用于响应master端,并进行通信-the slave I2C software, in response to the master terminal, and communications
clockv
- 使用Verilog语言编写的数字钟程序.有慢校时,快校时,闹钟等功能.-use Verilog language prepared by the digital clock procedures. Schools are slow, quick school, alarm clock functions.
DesignCompiler
- Design Compiler使用简要说明,说明了用这一工具进行综合的过程 -use Design Compiler brief statement, the use of this tool for integrated process