资源列表
STUDY_CPLD.RAR
- 这是可编程逻辑器件(CPLD)初学者的入门级文章,仅供参考。-This is the programmable logic device (CPLD), the entry-level beginners articles for reference purposes only.
SECLOCK
- 我从一本书上抄来的 但用MAX+PLUSII编译有些问题 初学者 见谅-from a book copied but with the MAX PLUSII compile some of the problems beginners forgiven
pci 的vhdl 源代码
- pci 的vhdl 源代码-The source code of PCI VHDL.
4x4的数据选择器
- 用vhdl的4x4的数据选择器,在maxplusII下编译、仿真通过。是构成大型数字电路的重要部件。适合vhdl初学者分析学习。-4x4 with the VHDL data selectors, under the maxplusII compiler, simulation through. Yes constitute large-scale digital circuits important components. VHDL Analysis for beginners to lear
Convolutional encoding and Viterbi decoding with k
- 卷积码编码和维特比解码 当K为7 时 供大家参考Convolutional encoding and Viterbi decoding with k 7 rate 1 2 -convolutional coding and Viterbi decoding when K 7:00 for reference convolutional encoding and Viterbi decoding with k 1 2 7 rate
cpld_bus
- CPLD的VerilogHDL总线代码,在EPM7128SLC84-10+Quartus4平台上运行通过.-CPLD bus Verilog HDL code, the PLD-10 Quartus4 platform to run through.
SPI串口的内核实现spicore
- SPI串口的内核实现spicore SPI串口的内核实现spicore-SPI string mouth essence realizes spicore the SPI string mouth essence to realize spicore the SPI string mouth essence to realize spicore
Music_altera
- 采用Verilog HDL设计,在Altera EP1S10S780C6开发板上实现 选取6MHz为基准频率,演奏的是梁祝乐曲 - Uses Verilog the HDL design, development board realizes in Altera on the EP1S10S780C6 selects 6MHz is the datum frequency, the performance is Liang wishes the music
second&clk
- 开发系统上采用的时钟信号的频率是20MHz,可分别设计计数器对其计数,包括计秒、分、小时、日、周、月以及年等。在每一级上显示输出,这样就构成了一个电子日历和时钟的模型。为了可以随意调整计数值,还应包含设定计数初值的电路
qdq_new
- 采用Verilog HDL设计,在掌宇智能开发板上得到实现 根据抢答器的原理,整个电路可划分为三部分:采样电路、门控电路和译码电路- Uses Verilog the HDL design, obtains the realization basis on the palm space intelligence development board to snatch the answering principle, the entire electric circuit may divi
ClkScan
- 此设计采用Verilog HDL硬件语言设计,在掌宇开发板上实现. 将整个电路分为两个子模块,一个提供同步信号(H_SYNC和V_SYNC)及像素位置信息;另一个接收像素位置信息,并输出颜色信号。这样便于进行图形修改,同时也容易实现- This design uses Verilog the HDL hardware language design, realizes on the palm space development board Divides into two stature
UART设计参考
- 软 件 设 计 者 必 看 UART 设计 参考-software designers Watchable UART reference design