资源列表
add_full_n
- 该程序实现的是n位全加器，首先用与非门实现一位全家器，最后实现n位的全加器。-the program is to achieve the n-bit full adder, first using the door with non-realization of a family - and finally realize the full n-bit adder.
发布15个Altera的IP的源码
- ALTERA的FPGA的IP核的源代码,为使用ALTERA的FPGA的相关设计提供参考.-Altera FPGA IP core of the source code for the use of Altera FPGA design to provide the relevant information.
ref-sdr-sdram-verilog
- 本代码是用VRILOG语言写的SDRAM的控制器的标准代码,供开发SARM参考.-this code is used to write the language VRILOG SDRAM controller standard code for the development of SARM reference.
CPLD的跑馬燈
- cpld的入门交流：CPLD的跑馬燈一个简易型cpld试验电路用VHDL语言遍的-cpld entry exchange : CPLD 5,250 cpld an easy-to-use test circuit using VHDL times the
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CH8CH4CH2CH1VHDL 数字电路参考书所有程序8
- CH4CH2CH1VHDL 数字电路参考书所有程序8-CH4CH2CH1VHDL digital circuit reference all proceedings 8
CH7CH4CH2CH1VHDL 数字电路参考书所有程序7
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CH6CH4CH2CH1VHDL 数字电路参考书所有程序4
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CH5CH4CH2CH1VHDL 数字电路参考书所有程序5
- CH4CH2CH1VHDL 数字电路参考书所有程序5-CH4CH2CH1VHDL digital circuit reference all proceedings 5
CH4CH2CH1VHDL 数字电路参考书所有程序4
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CH3CH2CH1VHDL 数字电路参考书所有程序3
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CH2CH1VHDL 数字电路参考书所有程序2
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