搜索资源列表
BCD_adder
- 基于FPGA的二进制加法器,简单易懂,适合初学者理解和接受。-Binary adder based on FPGA, simple, suitable for beginners to understand and accept it.
Chapter15-Adder
- 书籍《精通Verilog HDL语言编程》中第15章的程序实例代码,是关于常用加法器的设计的,对于初学者有一定的帮助-Books "Proficient in Verilog HDL language programming" in Chapter 15 of the procedure code, common adder design have some help for beginners
A-4-bit-variable-modulus-counter
- 用Verilog HDL设计一个4bit变模计数器和一个5bit二进制加法器。在4bit输入cipher的控制下,实现同步模5、模8、模10、模12及用任务调用语句实现的5bit二进制加法器,计数器具有同步清零和暂停计数的功能。主频为50MHz,要求显示频率为1Hz。-A 4-bit variable modulus counter and a 5bit of binary adder using Verilog HDL design. 4bit input under the control
UDP
- 这是用Verilog HDL编写的程序 利用UDP方法实现四位加法器-This is written in Verilog HDL programs Use UDP method four adder
addr_rtl
- 利用Verilog HDL编写程序 利用assign语句实现加法器-Use Verilog HDL to write programs Using the assign statement adder
jiafaqi
- 加法器 使用java代码编写简单的加法运算器 适合初学者-Adder suitable for beginners to use Java code to write simple adder
lab1
- 一个21位先行进位加法器的代码 交作业和毕设必备,自己写的,不完全地方请指出 -A 21-bit carry-lookahead adder code homework and must complete set up, wrote it myself, not exactly place please indicate
h2
- 加法器 输入信号: 输入数实部Ra,Rb,Rc,Rd,虚部Ia,Ib,Ic,Id的数据宽度均为19位;每次向加法器阵列只能送一个操作数,包括实数R(19bit)、虚部I(19bit);操作数据a、c、b、d的顺序连续送入,在加法器列中要进行串并变换。 CP脉冲。 输出信号: 输出数实部Ra’,Rb’,Rc’,Rd’,虚部Ia’,Ib’,Ic’,Id’的数据宽度均为21位。-Adder input signal: the real part of the input numbe
project3_1
- 逐次进位加法器,HDl verilog语言编写,能在DE2上运行-Successive carry adder, HDl verilog language, able to run on the DE2
jiafaqi
- 用Java实现的加法器,可以打开直接使用,方便,简洁-Java implementation of the adder available
ADDER
- 51单片机,加法器,包括键码扫描、储存、LED显示,有退格修改功能-51, adder, including key code scanning, storage, LED display, there is the backspace editing features
jianyijiafaqi
- 采用MAX+PlusII工具编辑设计的Verilog程序设计的简易加法器。可实现10以内的加法计算-Using MAX+PlusII tools to edit the design of Verilog design of a simple adder. Can be realized within 10 addition calculation
JAVA--Adder
- 可用于数字计算的小型加法器 使用JAVA语言编写-Can be used for digital computing small adder using JAVA language
add4_fast_carry
- 一个4位超前几位加法器的设计,在modelsim中仿真通过。-This is a carry lookahead adder design, which is simulated successfully in modelsim.
ADDER8B
- 用VHDL描述了八位加法器,并通过波形仿真验证其正确性-Described in VHDL eight adder and verify its correctness by means of simulation waveform
VHDL_book2
- add4a:4位加法器的设计 add8a:8位加法器的设计 subtract:4位减法器的设计 addsub: 4位加法器/减法器的设计 shift4:移位寄存器的设计 mult4:乘法器设计 div8:除法器设计 alu4:算术逻辑单元ALU设计-add4a: 4-bit adder design add8a: 8 bit adder design subtract: 4-bit subtraction Design addsub: 4-bit ad
vhdl1
- 该程序实现了运用VHDL实现数字音频滤波,同时在FIR 滤波过程中减少了加法器和乘法器使用数量,大大减小了内存-The program implements the use of VHDL digital audio filtering, while in the FIR filtering process to reduce the number of adders and multipliers used, which greatly reduces the memory
ripple_adder8
- 这是一个简单的8位行波进位加法器的verilog代码,可以综合。-The code implement ripple_adder.
EX8
- 累计进位加法器和超前进位加法器,数字逻辑课程作业-Cumulative carry lookahead adder and adder, digital logic course work
carry_chain_adder
- 第15章 常用加法器设计 样例程序-Chapter 15 Common Adder sample program