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frequency_counter44
- 采用多周期测量原理，即用标准频率信号填充整数个周期的被测信号，从而消除了被测信 号+1的计数误差，其测量精度仅与门控时间和标准频率有关，克服传统的直接测频或者直 接测周法均不能全面满足高精度要求的缺陷-Using the principle of multi-cycle measurements, i.e. integer number of cycles of the measured signal is filled with a standard frequency signa
mipsfiles
- 多周期的cpu 中alu模块设计 打算打打msn代码三年大开杀戒-cpu alu
winmips64
- winmips64是MIPS汇编的工具，根据汇编代码，可以单周期或者多周期运行，结果直观，功能强大-winmips64 is MIPS assembly tools, according to the assembly code, you can single-cycle or multi-cycle operation, the result intuitive, powerful
coa
- 在Modelsim中实现类MIPS多周期流水化处理器-In Modelsim achieve class multi-cycle pipelined processor MIPS
multi-CPU
- Verilog开发的能下载到FPGA实验板上运行的多周期CPU-Verilog can be downloaded to the FPGA development board running experiments multi-cycle CPU
multi_cpu
- 用xilinx ISE 14.3开发的多周期CPU系统，开发语言为verilog HDL.仿真调试与实际测试均已通过-Using xilinx ISE 14.3 development of multi-cycle CPU system, development language for verilog HDL. Simulation debugging and practical tests have passed
MIPS-and-CPU-design-and-simulation
- 兼容MIPS指令集的CPU设计与仿真 处理器架构为多周期，指令用32为字长（取指占一个周期），4k的存储器（指令存储器和数据存储器分开），IO与存储器统一编制，能支持20条指令以上-MIPS instruction set compatible CPU design and simulation
radar2
- 1、 生成多周期线性调频信号，并对其进行频谱分析； 2、 对仿真生成的信号利用两种窗口函数进行STFT变换生成时频分析图-1, to generate multi-cycle chirp signal, and its spectrum analysis 2, the signal generated by the simulation window function using two STFT transform to generate time-frequency analysis
muCPU_final
- 用Verilog开发的多周期CPU,可执行mips汇编中的R\I\J型指令，具有较高的参考价值。-Using Verilog development of multi-cycle CPU, mips executable compilation of R \ I \ J-type instruction, with a high reference value.
micro-op_cpu
- MIPS 微程序多周期cpu，mips的部分代码实现-MIPS cpu micro-program multi-cycle
Frequency-measurement
- 频率测量vi，包括ESTI、比例法、多项式逼近法、多周期平均计数法、仿真信号源、能量矩平衡、频率跟踪、三点法-Frequency measurement vi, including ESTI, ratio method, polynomial approximation method, average more cycle counting method, the simulation signal source, energy moment balance, frequency trackin
SRC
- 设计一个32位MIPS多周期微处理器 算数指令：ADD/ADDU/SUB/SUBU/ADDI/ADDIU 逻辑指令 移位指令 条件分支指令 无条件分支指令 数据传送指令-Design a 32-bit MIPS microprocessor multi-cycle arithmetic instructions: ADD/ADDU/SUB/SUBU/ADDI/ADDIU logic instructions shift instruction conditional br
MIPSCPU
- 这是verilog实现的MIPS多周期CPU在modelsim下面仿真通过-This is achieved verilog CPU MIPS multi-cycle simulation in modelsim below by
multi_cpu
- 用verilog语言编写的简单多周期CPU代码，在Sparten3板上可运行。实现了加、减、与、或、非等MIPS指令。-Verilog language with a simple multi-cycle CPU code can be run in Sparten3 board. Realization of add, subtract, and, or, not, etc. MIPS instruction.
minichartsPhoto
- 本系统安装于MT4平台中，适用货币对为EURUSD GBPUSD USDJPY AUDUSD USDCAD USDCHF。本系统的可以在指标窗口显示多周期的迷你图表，这样对交易者而言可以一目了然的实现了直观的行情判断，系统主要有均线迷你图多周期；STOCH（KD）指标多周期；MACD指标多周期显示等众多功能，系统模板默认为均线系统多周期汇客中国整理出来免费共享给大家，软件截图如下：
computer-composition
- Verilog在FPGA上实现多周期流水线带forwarding和hazard检测(如果你是学弟，为你着想，请不要直接copy)-Verilog on FPGA implementing a multi-cycled CPU with forwarding and hazard test
12061226project8
- 基于VHDL的多周期cpu模拟，北航作业，已检测可以运行。-cpu simulator
lab1_multicycle_dds
- 生成一个多周期直接信号数字合成器的Verilog代码，已在matlab中测试生成信号的频谱纯度符号要求-Generate more than one cycle of the signal direct digital synthesizer Verilog code, has been tested symbol require spectral purity of the signal generated in matlab
start_lab4
- 用Verilog设计一个时间基准电路和带使能的多周期计数器，并在此基础是设计一个简单的秒表0.0-10.0计数- Verilog design with a time reference circuit and with enable multi-cycle counter, and on this basis is to design a simple stopwatch count 0.0-10.0
CPU
- 使用Verilog HDL语言完成一个简单的多周期MIPS微处理器的设计-Using Verilog HDL language to complete a simple multi-cycle MIPS microprocessor design