搜索资源列表
aescore
- 基于FPGA的AES算法实现的VERILOG源代码,对于信息安全专业研究AES算法的硬件实现很有用-FPGA-based AES algorithm implementation VERILOG source code, for the information security professional research of the hardware implementation of AES algorithm is useful
16FFT
- 基于FPGA的16点FFT实现VEILOG-FPGA 16FFT VERILOG
opencore
- 基于FPGA的视觉采集系统的实现,verilog源码-FPGA-based visual collection system, verilog source
ps2_mouse_interface
- ps2接口的鼠标与vga接口的驱动程序,Verilog HDL语言,运用于FPGA-ps2_mouse_interface and vga in Verilog HDL language, applied to FPGA
fpgajpeg
- fpga实现图像的压缩,适合初学者,很快了解图像压缩和verilog-fpga to achieve image compression, suitable for beginners, will soon understand the image compression and verilog
MEDIAN.v
- fpga 的 median的verilog实现-median of verilog implementation
ARMcore
- 基于FPGA的ARM IP核!该软核VHDL源码全部开放-FPGA-based ARM IP core! The soft core VHDL source code are all open
ad_da_ctr
- 基于FPGA的ad和da转换Verilog代码,FPGA采用ep2c5芯片,做成异步fifo,ad芯片采用TI的ths1230,da芯片采用TI的TLV5619,仿真结果基本正确。-FPGA-based ad and da conversion Verilog code, FPGA using ep2c5 chip, made ??of asynchronous fifo, ad-chip using TI s ths1230, da chip uses TI s TLV5619, simula
zigbee_sensor
- ZigBee无线模块实验.rar;基于FPGA-2C35核心;博创实验箱平台。 在quartusII里面添加uart核,利用串口与主控制机相通信,获取从控制机上传感器的的温度、湿度、光敏电阻、热敏电阻等信息(其中主控制机与从控制机是通过zigbee协议通信) -ZigBee wireless module experiment rar core on the FPGA-2C35 Borch experimental box platform. Add uart nuclear qua
yindaiao
- Verilog HDL语言,在FPGA开发板上实现电子琴弹奏的功能-Verilog HDL language, in the FPGA development board to achieve the functions of keyboard play
dds
- 基于FPGA的DDS设计,本程序采用verilog HDL语言编写,使用DDS+Pll倍频-The DDS-based FPGA design, the procedures used verilog HDL language, the use of DDS+ Pll frequency
DDS
- DDS文件夹内的程序,完成直接数字频率合成功能,有正弦,三角,方波三种波形,并能扫频. 可通过键盘操作设置频率参数和选择波形种类和控制运行. 由两部分组成,"C"文件夹内,是用于在 51 单片机上运行的 C语言程序, "Verilog"文件夹内,是用Verilog语言编写的 FPGA 程序.-DDS program folder, complete direct digital frequency synthesis function, sine, triangle, square
RS-code
- 我测试过的!Verilog HDL实现RS编码。-I' ve tested it! RS coding Verilog HDL implementation.
pal_vedio
- 基于FPGA的pal制模拟视频显示程序,verilog Hdl-pal-d vedio display fpga verilog
ug_ram
- RAM design for FPGA in verilog
DSSS
- 基于FPGA的我直接扩频序列发射机的quarters代码,-direct sequence transmitter
UART
- 语言:verilog语言 功能:通过串口控制模块,实现FPGA与串口 通信。 仿真环境:modelsim 综合环境:quartus -Language: verilog language function: through the serial port control module, FPGA and serial communication. Simulation Environment: modelsim integrated environment: quartu
IEEE_Verilog_2001
- Verilog 2001 编程规范,作为ASIC和FPGA逻辑开发人员学习不可多得的资料,也可以作为逻辑开发高手们学习查阅的工具。新手们可以按照实例自己编程操练。
beep
- verilog写的控制喇叭的FPGA程序。-written in Verilog FPGA speaker control procedures.
usbFPGAconnect
- 该例程是PC机通过FX2-CY7C68013-A的USB2.0控制芯片与FPGA实现通信。其中的工程和代码包括PC机上的USB固件程序、驱动程序、上位机程序,FPGA上的VERILOG通信程序。-The routine is a PC, through the FX2-CY7C68013-A of the USB2.0 controller chip and the FPGA to achieve communication. One of the projects and code, incl