搜索资源列表
acc8
- VHDL语言设计八位加法器,可用于CPU中的加法模块,-VHDL language eight adder, adder module can be used for the CPU,
adder
- 基于FPGA的加法器的设计,QuartusII编译通过,采用VHDL语言编写。-The adder on FPGA design, QuartusII compile, USES the VHDL language.
Taddd_32_bbcdh
- 此程序源码使用VHDL语言,完成在32位十六进制加法器的基础上将输出出进行BCD码转换,实现输出是BCD码的32位二进制加法 可直接使用。 -This program source code using VHDL language, completed on the basis of 32-bit hexadecimal adder output BCD code conversion, the output is a 32-bit binary adder BCD code can be
fudian_add
- 用VHDL实现32位浮点加法器,结合乘法器具体实现用与快速傅里叶变换中。-use VHDL to finish the add device.
fudian_sub
- 实现32位浮点减法器,具体结合加法器和乘法器来实现快速傅里叶变换。-use VHDL to finish the sub device.
fudian_mul
- 实现32位浮点减法器,具体结合加法器和乘法器来实现快速傅里叶变换。-use VHDL to finish the sub device.
jiafaqi
- 利用FPGA,VHDL设计一个加法器控制LED。-The use of FPGA, VHDL design an adder control LED.
fVerrilog_Devr
- 朋友,我是Jawen.看到先前上载的一套CPLD开发板的VHDL源码挺受欢迎的,现在就将她的Verilog源码也一并贡献给大家:8位优先编码器,乘法器,多路选择器,二进制转BBCD码,加法器,减法器,简简单易懂状态机,四位比较器,7段数码管,i2c总线,lcd液晶LCD显示出来,拨码开关,串口,蜂鸣器,矩阵键盘,跑马灯,交通灯,数字时钟 可直接使用。 -Friends, I Jawen. See previous upload a CPLD Development Board VHDL so
adder_s
- 八位并行加法器,同时进位,利用VHDL语言,在ISE环境中建立工程-Eight parallel adder
adder
- 基于vhdl硬件描述语言的8位加法器的设计-Based on the design of the 8-bit adder VHDL hardware descr iption language
16
- 16位加法器,包括带符号的和不带符号的两种。基于vhdl编写。-16bit muntiplyer
adder
- VHDL语言编写,在实验箱上实现加法器的仿真,可行-VHDL language adder simulation experiment box, feasible
33-square-root
- 使用VHDL语言实现33位平方根进位选择加法器,能满足在500M时钟下正确工作,使用DB测试,并通过前仿。-Using VHDL language 33 square root carry select adder, to meet in the 500M clock work correctly, use the DB test, and through imitation.
four-adder-design
- 可编程逻辑设计-用VHDL语言进行四位加法器的设计-Programmable logic design _ four adder design
adder8b
- vhdl实现8位并行加法器,带进位,仿真没问题。-vhdl achieve 8-bit parallel adder with Carry the simulation no problem.
counter2b
- 基于vhdl完成4位计数器功能的实现,并基于此程序完成16位加法器程序的编写,内附testbench,测试成功。-Based on the vhdl completed four counter function to achieve, and the completion of a 16-bit adder program written based on this program, enclosing testbench, the test is successful.
jiafaqi
- 用VHDL语言实现对FPGA的程序编写,实现加法器功能。-FPGA program written using VHDL adder function.
pj
- 带有进位位的加法器、用vhdl语言编写。已通过quartusII编译-With the carry bit adder
add48
- 本历程时用vhdl实现对48位加法器的流水线设计,通过本程序可以了解流水线的设计方法,可以结合流水线的示意图度此程序。-The process of using vhdl 48-bit adder pipeline design, pipeline design can learn through this program, this program can be combined with the schematic diagram of the pipeline.
chaoqianadd6
- 用VHDL设计的超前六位加法器,实现六位二进制数的加法操作。-Adder VHDL design ahead of six, six binary addition operation.