搜索资源列表
jjj
- 实现了四bit计数器的功能，使用的是VHDL语言描述-Four-bit counter, using the VHDL language descr iption
32counter
- 用VHDL语言设计一个32位二进制计数器并进行功能仿真 2.用VHDL语言设计一个8位数码扫描显示电路 -A 32-bit binary counter design using VHDL language and functional simulation using VHDL language design an 8-bit digital scanning display circuit
counter2b
- 基于vhdl完成4位计数器功能的实现，并基于此程序完成16位加法器程序的编写，内附testbench,测试成功。-Based on the vhdl completed four counter function to achieve, and the completion of a 16-bit adder program written based on this program, enclosing testbench, the test is successful.
4_bit_counter
- 4位计数器 vhdl 源码 采用最少晶体管实现逻辑-4-bit counter
Digital-system-EDA
- 四位二进制数可预置可逆计数器设计 学习使用MAX+PlusⅡ文本编辑器的模板输入方法,熟悉常用语句的语法现象，掌握VHDL功能描述和结构描述的方法。-Four binary number can be preset the reversible counter design learning using a text editor MAX+Plus Ⅱ template input method, familiar with common statement syntax phenomenon
cnt10
- 基于vhdl的十进制计数器的设计，有计数的功能，是最基础的vhdl模块- Decimal
100jinshuqi
- 100分频计数器，已验证，作为vhdl初学者借鉴，也可在源程序的基础上进行修改-100 binary divider counter
sz
- 原创电子钟 VHDL语言 计数器原理 简单易懂 很有参考价值-Original electronic clock VHDL language counter principle straightforward great reference value
counter
- 用VHDL设计一个带加减功能的同步计数器-VHDL design a synchronous counter with addition and subtraction functions
The-various-functions-of-the-counter
- 各种功能的计数器VHDL语言编写，亲自运行，无错-The various functions of the counter VHDL language, personally run error-free
Decimal-Counter
- 十进制计数器（异步置数）及七段数码管显示系统，VHDL语言-Decimal Counter (Asynchronous Set the number) and the seven-segment LED display system, VHDL language
calculator
- 利用verilog和vhdl两种语言写作的计数器，还有个性化设计模块，利用quartusii平台写作。-Use verilog and vhdl counter writing in two languages, as well as personalized design module, using the platform quartusii writing.
CNT60
- 用VHDL设计了60的计数器，并用波形仿真验证了其功能-Design with VHDL counter 60, and a waveform simulation to verify its functionality
jishuqi
- 交通灯计数器设计，VHDL文件，搭载后续的文件程序可以构成完整交通灯程序。-Traffic light counter design, VHDL files, program files can be equipped with up to form a complete traffic lights.
shiyan_1
- 这是一个VHDL的程序，计数器程序实现输入输出从1到8的记数，完成这样的一个功能。-This is a VHDL program, program counter input and output from count 1 to 8, to complete such a feature.
qdq
- 用VHDL语言实现四路抢答器功能，抢答之后不能再抢答，除非主持人按下复位键。可以显示四个选手分数，显示答题倒计时的时间，主持人可以控制加减分，分数通过显示屏显示。使用软件Quartus Ⅱ，可以将程序导入FPGA并能运行。有竞争模块，显示模块，分频模块，加减控制模块，计数器模块，蜂鸣器模块，译码模块，计分器模块，锁定模块等。-VHDL language with four Responder function can not answer after answer, unless the hos
GAL
- 有关gal器件的编程入门，以及常见逻辑门、计数器VHDL程序-For gal device programming entry, as well as common logic gates, counters VHDL program
COUNT0
- 用VHDL语言编写的一种24位的计数器，带即时锁存功能，带清零、控制功能。已经经过仿真验证。-A 24 bit counter with the VHDL language, with instant latch function, with clear, control function. Has been verified through simulation.
Digital-clock-design
- 数字钟设计 用VHDL实现一个50MHZ到1HZ的分频器，利用Quartus II进行文本编辑输入和仿真硬件测试。实现一个60进制和24进制的计数器。测试成功。-Digital clock design using VHDL a 50MHZ to 1HZ divider using Quartus II simulation for text input and editing hardware test. Achieve a 60 hex and 24 hex counter. Test wa
counters
- 用VHDL编写的最大值为255的计数器，供初学者参考-A 255 counter of VHDL，for Beginners Reference