搜索资源列表
freedev_i2c
- FREEDEV数字应用开发板上的I2C总线IP核的verilog描述-FREEDEV digital application development board I2C bus IP core verilog descr iption of
user_logic_SEG7_LUT_8
- freeDev数字应用开发板中的七段数码管的IP核的verilog实现-freeDev digital application development boards in the seven-segment digital tube of the IP core implementation of the verilog
user_logic_VGA_Controller
- freeDev数字应用开发板中的VGA控制器的IP核的verilog实现-freeDev digital application development board of the VGA controller IP core implementation of the verilog
usb
- USB完整代码 包括vhdl和verilog两种-usb ip core
UART_IP_core_for_wishbone
- 基于wishbone总线的UART IP core-UART IP core based on Wishbone, generated in Verilog HDL.
FrequencyMeasureV1.0
- Verilog写的相检宽带测频的IP及文档。-Verilog of frequency measurement
dd
- ip megacore verilog 使用代码-ip megacore verilog using code
i2c_latest.tar_1
- I2C的OPEN CORE 的代码，很使用，可以直接改参数-I2C open core ip。verilog
RS232_NIOS_Verilog
- 5个文件，包含了RS232的nios实现和Verilog实现方式。其中,RS232的nios核实现只需要按照文件描述可以轻松实现^_^，个人比较推荐！RS232的Verilog实现需要编程，例程方便使用。RS232正在进一步学习中，有兴趣的可以探讨。-the realizition of rs232 interface by niosii uart ip core of Altera.it seems a most conveniet way.
serial
- 实现了一个串口功能，用Verilog语言写的，可作为IP使用-Implements a serial port function, written using Verilog language can be used as an IP
blk_write
- verilog 块ram写入操作 fpga xilinx ip core-Verilog block_ram module fpga xilinx ip core
i2c
- I2C IP CORE Verilog quartus-I2C IP CORE Verilog quartusii
source
- FPGA中实现I2C接口的一个IP核，包含verilog及VHDL代码。方便迅速理解和开发I2C总线接口。-FPGA to implement an I2C interface IP core that contains verilog and VHDL code. Facilitate rapid understanding and development of I2C bus interface.
pli_socket_example_pc
- vpi/pli socket example code-co-verification using TCP/IP socket (hardware model : verilog+ vpi as server) (software as a client)
IPcore_fifo_testbench
- 我自己写的一个verilog的fifo测试程序，配合xilinx的fifo ip核-I own the fifo write a verilog test procedures, with the fifo ip nuclear xilinx
usb2.0_funct_ip
- 一个USB2.0的IP核（详细verilog源码和文档），很不错的参考设计-A USB2.0 IP core (for details verilog source code and documentation), it is a good reference design
1_d_ff_bottom_top
- D flip flop,由verilog 以bottom_top 形式構成的IP電路模組 -the verilog of D flip flop bottom_top architecture
2_d_ff_top_dowm
- D flip flop,由verilog 以top down形式構成的IP電路模組 -D flip flop by verilog top down
USB_IP-CORE-design
- USB2.0的IP核，需要添加额外的PHY模块，使用Verilog语言编写-USB2.0 IP core, you need to add additional PHY module, using the Verilog language
epcs
- SOPC 系统集成编译的EPCS IP核 Verilog代码-EPCS IP core in SOPC