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- 完整的基于fpga的数字时钟的设计与实现，压缩文档是整个文档，其中的zzz，zzz1，zzz2，zzz3不同情况下的顶层原理图-Complete digital clock fpga based design and implementation, the archive of the entire document, which zzz, zzz1, zzz2, zzz3 different top-level schematic case
fenpin
- 18实验十八时钟分频1秒fpga的例子，代码分析很具体-18 experiments eighteen clock divider fpga example of one second
electric_timer_qutus
- 用verilog语言编写，主要是在FPGA中实现一个简易电子表的作用，利用时钟实现控制六个数码管的显示-With verilog language, mainly in the FPGA the role of a simple spreadsheet, use the clock to achieve control of six digital display
SIN_NEW1Hz
- 正弦波信号的产生,频率为1Hz,FPGA处理模块各部分所需工作时钟信号由输入系统时钟信号经分频得到，系统时钟输入端应满足输入脉冲信号的要求-generte sin wave, the frequence is 1Hz,FPGA processing module is required to work various parts of the system clock signal from the input clock signal by dividing the system clock
DDR2_test_Virtex5
- 针对于Virtex5 FPGA的DDR2读写测试的完整工程，2颗DDR2芯片的数据总线并接为32位，时钟200MHz-A full project for DDR2 test in Virtex5 FPGA board, with 32 bit data bus and 200MHz clock
led_0000_9999
- 基于FPGA，VHDL语言的数码管电子钟-Based on FPGA, VHDL language of digital tube electric clock
tiny64_latest.tar
- Descr iption Tiny64 A 64-Bit RISC CPU with minial resource usage. Every opcode is executed in 2 clock cycles. The word size is configurable via XLEN from 32 up to the FPGA limit. The assembler supports also differnet word sizes. Due simpli
vhdl
- 基于FPGA的实现一个电子时钟的VHDL语言-digital clock design with VHDL
digtal_clock
- 基于fpga的数字钟, quartus II 环境-digtal clock implement on fpga
digitron_driver_VHD
- 关于easy fpga开发板的led数码管的驱动； --输入：控制端ctrl_digin[2:0]共三位，表示（0~7）控制8个数码管的选通， -- 数据端dig_dtin[3:0]共四位，表示（0~F）控制数码管显示的数字 -- 控制时钟clk_dig一位用于时钟同步 --输出：显示dig_dtout[6:0]共七位，控制A,B,C,D,E,F,G[6:0]小数点不包括在内； -- 控制位ctrl_digout[7:0]共八位，任意时刻只能有一个为高，即只有一个
digitron_driver_V
- 关于easy fpga开发板的led数码管的驱动； 此为verilog程序 --输入：控制端ctrl_digin[2:0]共三位，表示（0~7）控制8个数码管的选通， -- 数据端dig_dtin[3:0]共四位，表示（0~F）控制数码管显示的数字 -- 控制时钟clk_dig一位用于时钟同步 --输出：显示dig_dtout[6:0]共七位，控制A,B,C,D,E,F,G[6:0]小数点不包括在内； -- 控制位ctrl_digout[7:0]共八位，任意时
AssignmentP6
- 1. For the VHDL model given below (Code List One), compare the FIFOs implementations on CPLD and FPGA. (1) Synthesize and verify (simulate) the VHDL design of the FIFOs (2) For CPLD implementation (fit) of the FIFOs, how many MCs (macrocells)
synchronism_design
- fpga中往往会遇到跨时钟，或者异步时钟，这就需要涉及到时钟的同步问题。-often will be in the fpga experience across clock or asynchronous clock, which relates to clock synchronization issues
1602_CLOCK
- 基于FPGA的1602时钟控制，支持时间调整-FPGA,1602 ,clock
FPGA_clock
- 使用VHDL语言在FPGA上完成数字时钟设计，可作为设计的参考-In the digital clock on the FPGA design using VHDL can be used as a reference design
shizi39
- 闹钟设计，基于fpga的多功能闹钟设计，时钟设计-Alarm clock design, design fpga-based multi-function alarm clock, clock design
verilog_sw_led
- 采用verilog编写的FPGA程序，程序的功能是按键按键消抖，quartus II 开发。芯片型号是EP2C35F484C7，时钟50MHz。-FPGA verilog to write the program, the program function is the key button is debounced, quartus II development. The chip model is EP2C35F484C7, clock 50MHz
dianzizhong
- 用FPGA实现多功能电子钟的全部程序，包括亮度调整，时间日期现实与调整，闹钟和秒表-FPGA implementation of multi-function electronic clock procedures, including brightness adjustment, the reality and adjustment of the time and date, alarm clock and stopwatch
watch
- FPGA实现电子钟功能，包括计时、显示日期、设定闹钟、切换12/24小时制等。-FPGA Implementation of the electronic clock function, including the timing, display the date, set the alarm, switch 12/24 hour system.
Bit_synchronization
- 这是一个位同步的FPGA完整代码，是用Verilog写的，其中包括分频、时钟、时钟提取等各模块以及顶层文件，做调制解调的朋友可以-This is a synchronous FPGA complete code is written in Verilog, including frequency, clock, clock extraction module and the top-level file, do the modulation and demodulation of a frien