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string
- 用verilog语言实现串口收发器设计，有详细代码-Serial Transceiver Design verilog language, a detailed Code
uart
- 用Verilog HDL，实现的FPGA串口调试程序，已经在硬件上调试成功-With Verilog HDL, FPGA serial debugger implemented in hardware debugging has been successful
value_to_ascii
- 使用Verilog HDL 进行数值与字符ASCII码的转化，实现串口正确显示字符，编程环境Quartus -Use Verilog HDL to numerically with ASCII characters transformation, realize serial display character correctly, Quartus ii programming environment
test_uart
- verilog 编写的串口发送和接收模块，能够设定停止位和校验位，并且包含了modelsim仿真文件。-verilog prepared by the serial port to send and receive module, capable of setting the stop bit and the parity bit, and includes modelsim simulation files.
Uart
- 使用verilog语言实现FPGA与计算机串口的通信，包括clk分频，uart顶层文件，rx，tx。使用verilog-FPGA serial port to communicate with the computer, including the speed choose, uart top file, rx, tx. Use Verilog
IIC_uart
- 本程序是用Verilog编写的，可实现IIC协议，同时联合串口uart通信，可实现pc机调试-The program is written in Verilog, enabling IIC protocol, while the United serial uart communications, enabling pc machine debugging
uart_ps2
- ps2接口的verilog module 负责用键盘发送数据，附带仿真task仿真，代码简单明了。 uart接口的verilog module ，通过PC机上的串口助手接收并显示键盘发送的数据 FPGA 板调试OK-ps2 verilog module with uart verilog module,fpga simulation ok.ps2 send data and uart get data and display in PC
verilog_UART
- verilog语言 FPGA 串口收发模块，既可以接收也可以发送，可以自行更改波特率-Verilog language FPGA serial transceiver module, I can receive can send also to change the baud rate
VerilogUart
- UART 串口通信模块，Verilog 实现。已在Microsemi Actel FPGA A3PE1500 硬件验证通过。-UART serial communication module, Verilog implementation. Verified by Microsemi Actel FPGA A3PE1500 hardware.
bldc_motor_control_design_example
- 无刷直流电机 VHDL VERILOG 控制,速度环，RS232 串口接收发送 始终分频 PWM生成 电机相序 actel FPGA使用-VERILOG BLDC control of the use of actel FPGA- actel VERILOG BLDC control of the use of actel FPGA
uart
- 用verilog语言编写的串口读写程序，波特率可调，亲测可用。-this is a program for UART by verilog, which is useful.
src
- verilog 通过串口控制VGA显示黑白机彩色棋盘 开发板是Xilinz RQ208-Color display in black and white machine control board through the serial port VGA Development Boards
receive_uart
- fpga串口通信，接收模块程序.verilog语言编写-fpga serial communication, receiving module program
uart_rx
- FPGA实现串口接收功能 Verilog语言-Serial reception FPGA Verilog language
uart_tx
- FPGA实现串口发送 Verilog 语言-Serial reception FPGA Verilog language.
asyn_fifo2
- 采用Verilog语言，使用FPGA内部IP核FIFO模块，实现串口的传输-Using Verilog language, the use of FPGA IP core internal FIFO module, serial data transmission
uartfifo
- fifo模式下的uart串口verilog的源程序-fifo mode serial uart verilog source
uartverilog
- 自动收发的verilog编写的uart串口程序-Automatically send and receive serial uart verilog written procedures
IIC
- IIC读写发送到PC串口的verilog源程序-IIC send the data to rs232 by pc
hdb3_v3
- Quartus环境下使用Verilog编写的串口程序，RTL和时序仿真已过-Quartus under the environment of a serial procedures written in Verilog, RTL and timing simulation has be passed