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ha1588_latest.tar
- IEEE1588源码verilog，运行可靠，可以很好地实现主机与从机的同步-IEEE1588 hardware language verilog
VerilogExemple
- verilog HDL语言的大量例程,内容详实，同步配套-The exemple is good to study verilog HDL language.to look!
ov_control
- ov7620CMOS控制的verilog代码，用vsync.href,pclk共同控制摄像头同步。在signaltap以验证-The verilog code ov7620CMOS control jointly control the camera using vsync.href, pclk synchronization. In signaltap to verify
fifo
- 同步fifo的verilog代码，很好的资料，值得学习-Synchronous fifo verilog code, very good information, it is worth learning
uart
- Verilog 编写全双工UART input clk, // 这个模块的主时钟 input rst, // 同步复位信号 input rx, // 串口接收端口 output tx, // 串口发射端口 input transmit, // 发送信号 input [7:0] tx_byte, // 发送的字节 output received, // 表明，已接受到一个字节 output [7:0] rx_
verilog_Manchester
- verilog—Manchester 极为简单的曼彻斯特编解码 verilog实现 分为编码和解码两个部分 通过自己测试 同步异步均正常收发-extremely simple verilog-Manchester Manchester codec verilog achieve synchronization through their own test is divided into two parts of the encoding and decoding Asynchronous w
FIFO_V1
- 同步FIFO和异步FIFO程序，希望对大家有用！verilog程序。-Synchronous FIFO and asynchronous FIFO procedures, and hope to be useful! The verilog procedure.
fifo-code
- Verilog代码：同步\异步FIFO。包含格雷码计数器.-Verilog code: syncronous\asyncourous FIFO. containing gray counter.
wei
- 位同步的verilog实现，利用窄脉冲来延迟或提前相位达到同步-Verilog achieve bit synchronization using narrow pulses reach synchronization to delay or advance phase
Pilot_Insert
- 导频插入，此程序用ISE的verilog编写，主要用于载波提取和采样频率同步-Pilot insertion procedures prepared by the ISE verilog, mainly used for carrier extraction and sampling frequency synchronization
Freq_counter_ise12migration
- 用verilog实现的一个频率计数器，可分别在不同的频率下计数（自己设定），里面有几个有用的小模块，分频，计数，显示，同步，进位等-Verilog to achieve a frequency counter, respectively, in different frequency count (set), there are several useful modules, divide, count, display, synchronization, binary, etc.
FIFO
- 三种同步方式实现的FIFO，verilog HDL，FPGA，更好理解FIFO-The three implemented synchronously FIFO, Verilog HDL, FPGA, a better understanding of the FIFO
A-4-bit-variable-modulus-counter
- 用Verilog HDL设计一个4bit变模计数器和一个5bit二进制加法器。在4bit输入cipher的控制下，实现同步模5、模8、模10、模12及用任务调用语句实现的5bit二进制加法器，计数器具有同步清零和暂停计数的功能。主频为50MHz，要求显示频率为1Hz。-A 4-bit variable modulus counter and a 5bit of binary adder using Verilog HDL design. 4bit input under the control
sync-and-asyn_FIFO_verilog
- 同步与异步FIFO的verilog实现，包括源代码，testbench，测试以及综合通过，还有相关参考资料-Synchronous and asynchronous FIFO verilog achieve, including source code, testbench, test and integrated through, as well as related references
gardner_test
- 无线通信中接收机的位同步，采用的gardner算法实现的verilog程序，需要自己综合编译-Wireless communication receiver bit synchronization algorithm used gardner the verilog program needs its own comprehensive compilation
test_pll_2
- 锁相环的verilog源代码，其中包括发送端，鉴相器，滤波器，压控振荡器的源代码，主要实现输入输出信号的跟踪，捕获和锁定，使输入输出信号在较短时间内达到同步。-This is a verilog code for PLL, including transmitor, PDF, Filter, VCO and so on. It mainly realize the input and output signal tracking, capture and lock, make the in
synchronous-FIFO
- 同步fifo的使用verilog案例讲解-The use of synchronous fifo verilog case to explain
syn_fifo
- 同步FIFO源代码，使用Verilog编写，用户可以轻松转换成VHDL。-Synchronized FIFO source code
exercise3
- 用verilog实现dsp与Fpga接口的同步设计，其功能包括读写操作及四个功能模块，采用两个fifo实现不同时钟域的地址与数据的转换，在quartus ii11.0环境下运行，运行此程序之前需运行将调用fifo。-Dsp using verilog achieve synchronization with Fpga interface design, its features include read and write operations and four functional modul
CP_adder
- 用verilog 语言实现数字通信中最先进的技术之一中的OFDM技术中的添加循环前缀，可以减少码间干扰，并实现符号同步-a great complied code of cyclic prefix for OFDM which is good for intersymbol interference and inter channel interference