搜索资源列表
io_uart
- verilog设计的32位IO口扫描后通过串口发送到计算机-Verilog design of 32 bit IO export after scanning through the serial port to the computer
UART_Transmitter_Arch
- 自己编写的带有FIFO的UART串口发送模块，代码通过状态机实现，开发语言是Verilog-I have written to the FIFO UART serial transmit module code through the state machine implementation, development languages Verilog
fpga_Uart
- 串口通信控制器 verilog实现含波特率发生模块，发送、接收模块程序以及xilinx所有工程文件-The serial communication controller verilog containing the baud rate generator module, send, receive module program xilinx all project files
FIFO
- 是用verilog HDL写的基于FIFO的串口发送机的设计，很详细的代码，很值得学习，已经验证通过-With verilog HDL based on FIFO serial transmitter design, write code, it is worth learning, has been verified by.
verilogUART
- verilog实现的串口实现代码，可以直接复制使用-verilog achieve serial implementation code can be copied directly use
rxd
- 用verilog实现的串口接收程序，仿真通过-Verilog implementation receiver program, through simulation
txd
- 用verilog实现的串口发送程序，和之前的发送程序可以一起使用，仿真通过-Verilog achieve serial transmission program, and before sending program can be used in conjunction with simulation through
uart16550_latest.tar
- UART16550是较为通用的串口协议，压缩包内有4个文件可供选择，直接提供RTL源码，可直接导入到工程内。-Uart16550 core is used for Serial Commuication.There are 4 folders in the zip package and have the verilog RTL which can be added in the project.
fpga
- FPGA的串口+计数器+DPS+数模转换的VERILOG源代码。-The VERILOG source of digital-to-analog conversion of the FPGA serial the+ counter+DPS+ code.
serial
- Verilog HDL编写的串口通信程序。-The Verilog HDL written serial communication program.
async_transmitter
- 使用Verilog编写串口发送16bits，内含补码运算；参数化编写。-verilog uart 16bits transmitter two s complement parameter code
rs232_verilog
- FPGA实现串口通信实验，用verilog实现串口的发送和接收数据-FPGA Implementation of serial communication experiment, the serial port to send and receive data with verilog
RX_FARM_24_DATA
- verilog代码，串口接收程序，有协议-Verilog code, the receiver program, agreement
uart_Verilog
- 基于Verilog的RS232串口通信实验，可发送256位数据，并在Altera的EP4CE15F17C8芯片上验证成功。-Verilog-based RS232 serial communication experiment, 256-bit data can be sent on Altera' s EP4CE15F17C8 chip authentication is successful.
uart_state
- 基于状态机编写的串口通信实验，编程语言是Verilog HDL，可发送八位数据，在Altera的EP4CE15F17C8芯片上验证成功。（与另一个发送256位不同的是这个代码比较突出状态机的使用）。-Prepared by the serial communication experiment based on state machine, the programming language is Verilog HDL can transmit eight bits of data, verif
verilog_rs232_rx_tx
- fpga中verilog实现的rs232串口收发逻辑，基础入门，参考学习串口收发-FPGA in Verilog implementation RS232 serial port transceiver logic, based on entry, refer to the study serial transceiver
UART
- UART --串口发送与接收verilog代码，适用于QUATUS II 开发环境下，适合verilog入门的学员-UART- on serial port ,send and receive signal, suitable for QUATUS II development environment for Verilog entry students
ICAP_FPGA_Multiboot
- 在xilinx的ml507板子上用的ICAP功能 配置存储器 这里边包含了控制程序 以及配置ICAP寄存器的程序 就是完整的通过串口控制FPGA多重配置的程序 用verilog实现的-how to configure the ICAP
communication_232
- FPGA 串口程序 VERILOG-FPGA serial procedures
my_uart
- 本程序采用Verilog HDL程序编写的串口程序。-The program uses the Verilog HDL programming serial procedures.