搜索资源列表
address_gen
- 基于FPGA使用Verilog语言构成的DDS信号发生器-DDS signal generator based on FPGA using Verilog language constitutes
AD9854verilog
- verilog 编写的AD9854配置代码 通过状态机转换来配置AD9854-CONGIURE the ad9854 dds
LSY_wave
- 比赛时写的李萨如波形发生器的代码,用verilog写的,里面集成数据采集和DDS波形发生。-Game when writing the the Lissajous waveform generator code, written in verilog the inside integrated data acquisition and DDS waveform generation.
Pro_19
- Fpga,DDS,PLL,rom(正弦波)(f<13MHz,需要滤波)(Verilog)-Fpga, DDS, PLL, rom
Regtangle_wave_DDS
- 利用VERILOG编写的DDS产生方波的程序-Using VERILOG written DDS program produce a square wave
Sender
- 直序扩频通信发送部分的源代码,用verilog编的,包括信源模块、扩频模块、极性变换模块和DDS调制模块-Direct sequence spread spectrum communication sent part of the source code, compiled with verilog source modules, spread spectrum modules, polarity transform module and DDS modulation module
ad9850
- 介绍了用FPGA控制DDS产生任意频率范围之内的可调制正弦波,13位BPSK,ASK等。控制字由串口写入。-verilog control AD9850 to get psk ask
qam_64
- Verilog语言下QAM调制的DDS实现-The QAM Modulation DDS achieve
No.2DDS
- 用Verilog HDL实现DDS信号发生器。-DDS signal generator using Verilog HDL.
5-15
- 用verilog语言实现基于DDS技术的余弦信号发生器,其输出位宽为16比特-Verilog language cosine signal generator based on DDS technology, the output bit width is 16 bits
signal-generator
- Design of DDS signal generator based on VHDL+FPGA, has been through the adjustable, can be directly used, simulation -DDS signal generator circuit design, Verilog source code, can be directly used, simulation
dds_work
- verilog语言编写,在Quartus II里仿真DDS的产生,包括所有仿真生成的相关文件--verilog language in the Quartus II DDS in the generation of simulation, including all documents generated by the simulation,
DDS_dac9764
- verilog语言编写的DDS信号源,采用DAC9764-verilog DDS signal source language, using DAC9764
dds_double_new
- FPGA用verilog语言编写的 dds程序,两路输出,频率可调,相位可调,输出波形可调-FPGA using verilog language dds program, two outputs, adjustable frequency, phase adjustable, adjustable output waveform
DDS_Ad9854_Verilog
- DDS控制模块 AD9854 VERILOG-DDS control module AD9854 VERILOG
dds_compiler_v4_0
- Verilog的DDS实现正弦波输出。这个模块是不可综合的,但是已经综合了,-Verilog DDS
DDS_TLC5620
- DDS函数信号发生器 tlc5620 verilog-dds tlc5620 verilog
sss
- 使用Verilog语言编写源代码.调用一些基本的IP核,如DCM模块、DDS模块ChipScope模块、乘法器模块等来实现调制.最后通过编程并利用FPGA板子实现AM、DBS、SSB的调制。-Using Verilog language source code. Invoke some basic IP cores, such as DCM module, DDS module ChipScope modules, multiplier module to achieve modulation.
module-counter8
- 用verilog实现8为计数器频率范围20-80kHz,根据DDS原理来一个时钟计数器记一下,n=n+1,根据公式fout=(fc÷x)÷2,fout=80 fc=320,所以n≥2时,再取反,又由公式 fout=(k.fc)÷2^n,k=50hz,fout=80khz,fc=320,所以数据的位宽n≥7。 设计要求两路方波信号的相位差在0-360゜可调,可以根据延时来实现。具体的-8 is realized with verilog counter frequency range 20-8
Codes-and-Reports
- Verilog Source code for arbitrary waveform generator- simple DDS algorithm codes run on Xilinx Spartan-3E fpga to show output on dac pin. Please see the included report. its really simple to implement. all source code is given.