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uart8.zip
- 使用Libero提供的异步通信IP核实现UART通信，并附带仿真程序。UART设置为1位开始位，8位数据位，1位停止位，无校验。且UART发送自带2级FIFO缓冲，占用FPGA面积很小。,Libero provided the use of asynchronous communication IP core implementation UART communications, and incidental simulation program. UART is set to 1 to sta
uartvhdl
- VHDL语言实现的UART IP核，比较实用-VHDL language to achieve the UART IP core, more practical
uart2bus
- uart接口到内部总线的IP核，采用VDHL和VERILOG语言编写。-UART interface to Bus IP Core in VHDL and verilog languages
uart_serial
- UART IP core in VHDL
UARTipcore
- 这是一个关于UART的IP核，用VHDL写的。经过本人的鉴证，非常实用并且写的非常好。-This is one of the IP core on the UART, using VHDL written. After my verification, very practical and very well written.
uart16550_latest[1].tar
- 开源UART IP核16550，该IP核兼容16550 UART，具有Modem功能，完全可编程的串行接口具有可设置的字符长度、奇偶校验、停止位以及波特率生成器。-Open-source UART IP core 16550, the IP core is compatible with 16550 UART, with Modem function, fully programmable serial interface can be set up with a character lengt
fifoed_avalon_uart9.1_applicaton
- 用于Altera Avalon总线的、具有FIFO缓冲的Uart数据串口IP核以及应用于Nios2的、真正可运行的、容易移植的C代码。-Fifoed avalon uart IP core and C code for the IP core.
UART_IP_core_for_wishbone
- 基于wishbone总线的UART IP core-UART IP core based on Wishbone, generated in Verilog HDL.
RS232_NIOS_Verilog
- 5个文件，包含了RS232的nios实现和Verilog实现方式。其中,RS232的nios核实现只需要按照文件描述可以轻松实现^_^，个人比较推荐！RS232的Verilog实现需要编程，例程方便使用。RS232正在进一步学习中，有兴趣的可以探讨。-the realizition of rs232 interface by niosii uart ip core of Altera.it seems a most conveniet way.
UART
- 用硬件描述语言实现的uart的IPcore，有详细的注释和测试文件-Hardware descr iption language of the H.264 encoder, detailed notes and test files
uart
- uart IP CORE Verilog quartus-uart IP CORE Verilog quartusii
jtag_uart
- SOPC jtag uart 系统集成编译的IP核-Jtag-uart IP core in SOPC
FIFOED_UART
- CAL_UART核verilog源码，带FIFO，FIFO深度可设置。-fifoed uart ip core. cal_uart.
uart-IP-Core
- 串口的FPGA VHDL的IP核 可以直接调用使用-Serial FPGA VHDL IP core can be called directly use
UART
- 1.UART是一个UART的IP核，在其它的程序中可以直接的调用的,波特率是9600.-Is 1.UART a UART IP core can directly call the other program, the baud rate is 9600.
uart_latest.tar
- VERILOG串口IP核，在XC2S200E测试过-UART IP CORE
man2uart_latest.tar
- fpga uart串口ip核，源代码例程。-fpga uart ip core
UARTWISHBONECompatible---Downloads
- 16550 uart code lattice cpld fpga 已经验证-16550 uart ip core
UART-IP-based-on-queue
- 基于队列传输的UART的IP核程序，已调试可直接使用。-Queue-based transmission of UART IP core procedures have been debugging can be used directly.
uart_latest.tar
- UART的VHDL建模代码，是一个标准的IP核(UART's VHDL modeling code is a standard IP core)