搜索资源列表
aes
- 高级加密标准AES的FPGA实现，支持128，256密钥长度格式-Advanced Encryption Standard AES, FPGA implementation to support 128,256 key length format
RTC
- verilog编写的RTC（实时时钟）包含APB总线接口、时钟计时部分等-verilog prepared by the RTC (real time clock) contains APB bus interface, clock time some other
aes_thesis_v1.0
- AES VERILOG CODE 128 192 32DES比較-AES VERILOG CODE 128 192 32DES Comparison
i2cBUS
- I2C总线是一种非常常用的串行总线，它操作简便，占用接口少。本程序(verilog hdl)介绍操作一个I2C总线接口的EEPROM AT24C02 的方法，使用户了解I2C总线协议和读写方法。-The I2C bus is a very common serial bus, it is simple, occupy less interface. This program (verilog HDL) introduced operating a AT24C02 EEPROM of I2C
PCI9052
- 用verilog语言编译的pci协议实现，而且有具体的电路图-Compiled with the verilog language pci protocol implementation, but also the specific circuit
74LS160
- 源码，VHDL语言编写的74LS160计数器-Source code, VHDL language of the 74LS160 counter
SRAM_Proj
- SRAM 读写VERILOG HDL源码-SRAM read and write VERILOG HDL source code
CPU
- CPU的构造，采用veril语言 对计算机专业同学有用-CPU
stopwatch
- 数字秒表的VHDL代码。当设计文件加载到目标器件后，设计的数字秒表从00-00-00开始计秒。，直到按下停止按键（按键开关S2）。数码管停止计秒。按下开始按键（按键开关S1），数码管继续进行计秒。按下复位按键（核心板上复位键）秒表从00-00-00重新开始计秒。-The VHDL code for digital stopwatch. When the design document loaded into the target device, the designed digital stop
ARM
- ARM内核及性能比较(列表对比)包含arm7、arm9、arm9e、arm10e、arm11等-ARM core and performance comparison (list comparison) contains arm7, arm9, arm9e, arm10e, arm11, etc.
lpm_ram
- altera LPM_RAM的使用,有简单的程式和模拟结论.大家写的时候可以参考.-altera LPM_RAM the use of a simple programming and simulation findings. we can refer to when writing.
ovm-2.1.1
- OVM cookbook 配套程序 使用systemVerilog-ovm
Viterbi_Verilog
- For viterbi algorithm hardware implementation
ds18b20_verilog
- 用verilog语言编写，实现DS18B20测量温度的程序，包括整个工程文件。-Using verilog language, achieve DS18B20 temperature measurement procedures, and including the project file.
DA
- 采用Verilog在FPGA上实现一阶Σ-Δ DAC，仿真和实际验证都正确，基本可以达到16位DAC的信噪比
quaddecoder_verilog_ise11.2_used_09042010
- Two simple Quadrature decoder and Counter build in a XILINX XC9536 CPLD. This Core is coded in Verilog and contains the compete Project file and the fitted quad.jed File. The Pinout is descr ipted in the Constrained file quad.ucf. To use them, y
SinglecycleCPU
- 用Verilog实现一个简单的单周期CPU，并运行Quicksort程序以验证正确性。-This file is written in Verilog to achieve a single cycle processor. It can run in Quartus2.
onesecond
- 用verilog实现将50M晶振分频，得到1M的功能，本人已经用Quarter9.0运行成功。-To achieve with verilog 50M crystal frequency, get 1M' s functions, I have run successfully with Quarter9.0.
AD_CNTR4.4a
- 该程序是用vhdl控制max125进行ad转换的程序，已经在本人的板上调试通过。对于用vhdl编写ad转换程序有一定的参考价值。-The program is vhdl control max125 for ad conversion process, has been through in my board debug. Ad for the preparation of the conversion process using vhdl some reference value.
aips7108.tar
- SATA 仿真模型 SATA 仿真模型-Simulation Model SATA SATA SATA simulation model simulation model