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Four-controllable-counter
- 功能是（用Verilog语言的，内有比较详细的注释）： （1）计数器的功能是从0到9999计数，并能以十进制数的形式在七段数码管上显示出来(包括七段数码管显示模块). （2）该计数器有一个1个nclr和一个adj_plus端，在控制信号的作用下（见下表），计数器具有复位、增或减计数、暂停的功能。编写以上的程序的完整模块. 计数器的功能表 nclr adj_minus 功 能 0 0 复位为0 0 1 递增计数 1 0 递减计数 1 1 暂停计数 -Functi
LED_7seg
- FPGA的7段数码管程序，用verilog编写，很好的程序，不要错过啊-The 7-segment FPGA program written with verilog, very good program, do not miss ah
seg
- 这是用verilog 编写的静态数码管实验，初级，实用，挺好的例程-It is written in verilog static digital test, primary, practical, very good routine
7duanshumaguandejingtaixianshi
- 采用Verilog语言编写实现7段数码管的静态显示，经过CPLD开发板验证，程序正确-Verilog language used to achieve a static 7-segment display, after a CPLD development board verification, the program correctly
counter_SEG7
- 本程序是关于检测数码管与按键的verilog程序，在开发板上已运行成功-This program is about the detection of digital control with buttons verilog program has been running successfully in the development board
verilogshiyansoure37
- verilog实验的基本程序，包括状态机、数码管、流水灯、蜂鸣器、点阵、键盘等等，超详细的程序、适合初学者-verilog basic experimental procedures, including the state machine, digital control, water lights, buzzers, dot matrix, keyboard, etc., super detailed procedures, suitable for beginners
PS2controller
- 基于Verilog语言的PS2控制和显示程序，完成Basys开发板上对PS2端口的控制，和数码管显示-Verilog-based Voice of the PS2 control and display program, complete Basys PS2 port on the development board control, and digital display
SEG_Dynamic
- 数码管显示程序，采用Verilog语言编写，在开发板上经过验证，希望对大家有所帮助-Digital display procedures, the use of Verilog language, proven in the development board, we hope to help
SEG_static
- 数码管静态显示程序，采用Verilog语言编写，再开发板上经过验证，希望对大家有所帮助-Digital static display program, the use of Verilog language, and then validated the development board, we hope to help
verilog_calculator
- 一个Verilog写的简易计算器。能进行二进制加减乘除运算，操作数通过按键输入并用数码管显示。当按下运算符号键后，计算器进行两个数的运算，数码管将结果显示出来。-A simple calculator written in Verilog. Binary addition and subtraction to multiplication and division, operating a few keystrokes and use digital display. When the pres
dianzimimasuo
- 采用verilog设计，7段数码管进行输入的显示，在DE-2平台上进行密码锁的实现。-Using verilog design, 7-segment LED display for input in the DE-2 platform on the lock implementation.
05_ledtimer
- 数码管显示的时钟,verilog HDL 基础教程-a timer basied on led
velocity_Verilog
- 速度表（velocity）要求：1．显示汽车Km/h数；2．车轮每转一圈，有一传感脉冲；每个脉冲代表1m的距离；3．采样周期设为10s； 4．要求显示到小数点后边两位；5．用数码管显示；6. 最高时速小于300Km/h。（约为83.3m/s） -use verilog to realize velocity
top
- 在ISE环境里，用verilog语言编写得数码管显示程序，能动态计数-In the ISE environment, use the verilog language digital display program was able to dynamically count
matrixKeyboard_seg7
- 基于Verilog实现的矩阵键盘扫描和数码管动态显示-Verilog-based implementation of matrix keyboard scanning and LED dynamic display
led_seg
- 红色飓风 数码管累加Verilog 代码 初学者 共同学习-Red LED Hurricane cumulative Verilog code for beginners to learn together
jing-dain--FPGA-cheng-xu
- 关于FPGA的经典算法，包括数码管的编程和显示，用Verilog HDL语言写的程序，在开发板上已经测试成功！-Classical algorithm on the FPGA, including digital programming and display, using Verilog HDL language to write programs, the development board has been tested successfully!
DIG_LED
- 数码管的Verilog HDL高级描述，将数码管接口封装完成，适宜20MHz的时钟使用-Digital control of high-level Verilog HDL descr iption of a digital control interface, complete package, suitable for use 20MHz clock
timer
- verilog秒表fpga 4位数码管显示-verilog digital display stopwatch 4
source
- FPGA驱动八位数码管，做为16进制计数器。-16 counter,using verilog HDL