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Wishbone
- wishbone总线协议详细的技术说明文挡！-wishbone bus protocol detailed technical descr iption of the text block!
simple_spi
- 一个简单的ＳＰＩ ＩＰ核，SPI Core Specifications 可以从说明文档中找到！ The simple Serial Peripheral Interface core is an enhanced version of the Serial Peripheral Interface found on Motorola s M68HC11 family of CPUs. The Serial Peripheral Interface is a serial, synchron
open_cores_VGAcore
- 老外写的基于wishbone总线协议的VGA核控制器,Verilog版本适合于初学者学习VGA核控制器的原理以及总线协议的把握-Written by foreigners wishbone bus protocol based on the nuclear VGA controller, Verilog version is suitable for beginners to learn the principles of the controller and the VGA core gras
uart
- uart协议、实现、验证，基于wishbone协议，工业标准为16550A-UART protocol, implementation, verification, based on the Wishbone protocol, the industry standard for the 16550A
pif2wb_latest.tar
- This is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently supports single-cycle as well as burst transfer operations. The core has been tested in a master-PIF slave-WB configuration.-This is is a b
wb_conbus
- wishbone的verilog代码的实现，标准的协议规范-wishbone of the verilog code implementation, the standard protocol specification
i2c_latest[1].tar
- I2C is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange between devices. It is primarily used in the consumer and telecom market sector and as a board level communications protocol. The OpenCores I2C Mast
wishbone_vip
- wishbone protocol verification tool
SPI
- Verilog编写的SPI程序，含英文原文档说明，很全的-The OpenCores simple Serial Peripheral Interface core is an enhanced version of the Serial Peripheral Interface found on Motorola s M68HC11 family of CPUs. The Serial Peripheral Interface is a serial, synchronous comm
IDE_VHDL
- 此代码为wishbone公司的IDE协议主机端VHDL源代码，有三个版本，实现了UDMA。版权归wishbone公司，请勿用于商业用途。-This VHDL codes with threr versions implemented IDE host protocol，supporting with UDMA。
i2c_latest.tar
- i2C总线的控制器核，实现了I2C的主站功能。-I2C is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange between devices. It is primarily used in the consumer and telecom market sector and as a board level communications protocol
wishbone
- Wishbone规范具有如下特点:简单、紧凑，需要很少的逻辑门 完整的普通数据据传输总线协议，包括单个读写、快传输、读一修改一写周期、事件周期 数据总线宽度可以是8-64位 支持大端(big-endian)和小端(litle-endian)，接口自动完成两者之间的转换。支持存储器映射、FIFO存储器、交叉互联 握手协议，允许速率控制 可以达到每个时钟周期进行一次数据传输 支持普通周期结束、重试结束、错误结束等总线周期形式 支持用户自定义的标志:采用MASTER/SLAVE体系结构 支持多点进程(
dma_rtl
- 该代码实现了一个基于Wishbone总线协议的DMA控制器，由于SOC可集成的模块越来越多，本文设计的DMAC包含了31个可编程的DMA通道，能够处理多个DMA传输请求。由于数据在Wishbone总线上传输，在总线接口方面，本文设计的DMAC提供了两个既可以作为主机接口又可以作为从机接口的Wishbone接口。当有多个外设同时发出DMA请求时，本文设计的DMAC采用循环优先级和动态优先级相结合的方式，实现了通道仲裁器二级仲裁的功能。为了提高传输效率，本文设计的DMAC不仅支持数据块的传输，还支持