搜索资源列表
MutiplierDesign
- 流水线乘法器,vhdl语言描述, 希望对大家有所帮助 -pipelined multipliers, vhdl language, we hope to help
erweiDCT
- 用 FPGA实现了二维离散余弦变换和逆变换，结构设计采用行列分解法，乘法器采用移位求和的方法实现，并且采用流水线结构设计，提高处理核的性能-Using FPGA to achieve the two-dimensional discrete cosine transform and inverse transform, the structural design of the use of the ranks of decomposition, the sum of multipliers us
jiafaqi
- EDA条件下乘法器的实现。AHDL语言实现输入显示乘法等功能-EDA under the conditions of the realization of multipliers. AHDL language features such as input showed that multiplication
PLLpostprocesser
- this the phase locked loops post processer.PLLs are widely used in frequency synthesis, for frequency multipliers and dividers, for carrier and symbol synchronization, and in the implementation of coherent receivers-this is the phase locked loops pos
FIR_csd_mul
- 采用CSD编码的常系数乘法器的FIR滤波器的设计。-CSD-coded using constant coefficient multipliers of the FIR filter design.
002
- 读入两个乘数，赋给x，y变量 计算两个乘数的积，赋给变量输出结果 */-Read two multiplier assigned to x, y variables calculated the product of two multipliers, the output is assigned to the variable* /
lagrange-multiplier
- Larange Multipliers-Larange Multipliers...........
ga
- 电路演化，可以生成一个两位乘两位的乘法器-Circuits have evolved to generate a two by two multipliers
fVerrilog_Devr
- 朋友，我是Jawen.看到先前上载的一套CPLD开发板的VHDL源码挺受欢迎的，现在就将她的Verilog源码也一并贡献给大家：8位优先编码器，乘法器，多路选择器，二进制转BBCD码，加法器，减法器，简简单易懂状态机，四位比较器，7段数码管，i2c总线，lcd液晶LCD显示出来，拨码开关，串口，蜂鸣器，矩阵键盘，跑马灯，交通灯，数字时钟 可直接使用。 -Friends, I Jawen. See previous upload a CPLD Development Board VHDL so
multi_4
- 自己用写的VHDL的四位乘法器，实现方式比较简单-Write the VHDL four multipliers to achieve relatively simple way
EDA
- EDA课程设计，设计的四位乘法器，原理，仿真结果及其原程序。-EDA curriculum design, the design of the four multipliers, the principle of simulation results and its original program.
coding
- 数字通信系统设计上机实验题，二分频，全加器，乘法器，四选一选择器-Digital communication system design on the experimental questions, divide, full adders, multipliers, four elected a selector
vhdl1
- 该程序实现了运用VHDL实现数字音频滤波，同时在FIR 滤波过程中减少了加法器和乘法器使用数量，大大减小了内存-The program implements the use of VHDL digital audio filtering, while in the FIR filtering process to reduce the number of adders and multipliers used, which greatly reduces the memory
9_6
- 介绍一个包含编辑框控件的“乘法器”程序，使用者在“乘数”或者“被乘数”编辑框输入数字的时候，程序可以随时计算乘法的结果-Introduction of an edit control that contains " multipliers" program, the user " multiplier" or " multiplicand" edit box enter a number, the program can be readily
booth_multiplie_module
- 利用verilog实现的Booth算法乘法器，对想学习乘法器的将会有很大的帮助.-Booth algorithm verilog realization use multipliers, the multiplier will want to learn a great help.
ga
- 电路演化，可以生成一个两位乘两位的乘法器-Circuits have evolved to generate a two by two multipliers
VMD_1D
- Spectrum-based decomposition of a 1D input signal into k band-separated modes. Here, we propose an entirely non-recursive variational mode decomposition model, where the modes are extracted concurrently. The model looks for an ensemble of modes and t
code
- Due to its high modularity and carry-free addition, a redundant binary (RB) representation can be used when designing high performance multipliers. The conventional RB multiplier requires an additional RB partial product (RBPP) row, because an err
计算器
- 简易计算器,可以用于加减乘数等运算，适合课程作业借鉴(Simple calculator, can be used to add and subtract multipliers and other operations, suitable for the course operation reference)
Meher_2014.pdf.tar
- his work describes an approximate DCT architec- ture for the High Efficiency Video Coding (HEVC) standard. Since the standard requires to support multiple block sizes, architectures based on exact implementation require a relevant amount of hardw