搜索资源列表
FULLADD
- Full adder using Verilog
verilog
- 里面包含了多个verilog源代码例子 包括循环码编解码、加法器等等常用的例子 -Which contains a number of Verilog source code examples include the cyclic code coding and decoding, and so on commonly used adder example
bitadder
- 一位全加器，VERILOG实现，包括测试文件，测试可用，欢迎下载，共同学习-A full adder, VERILOG implementation, including test papers, test available, please download, a common study
save_adder
- implement of carry save adder with verilog
lookahead
- implement of carry look ahead adder vith verilog
adder
- 此程序是用verilog语言编写的8位加法树乘法器，这种乘法器速度快，可以实现一个周期输出一个结果…-This program is written in verilog language 8-bit adder tree multiplier, the multiplier speed and the ability to achieve a cycle of output of a result ...
adder_4
- 详细介绍了四位加法器的verilog代码，还包括详细的testbench代码。-Details of the four adder verilog code, also includes detailed testbench code.
full_a4
- 4位全加器的verilog程序设计-Four full adder verilog programming ...
adder
- 包含32位有无符号数的加减法，verilog语言描述，加法器分别采用行为级描述、行波进位、平方根进位三种描述方法，并有简单的testbench-32bits adder with addition and subtraction function. verilog HDL language . three kinds of implementations: adder behavioral descr iption, ripple carry, the square root of the ca
4weichaoqianjinweiqi_verilog
- 四位超前进位加法器的verilog实现。用VHDL语言，附加检验tb.v-Four lookahead adder verilog implementation. VHDL language, additional testing tb.v
4weizhucijinweijiafaqi_verilog
- 四位逐次进位加法器的verilog实现。附tb.v文件。单片机开发，数字逻辑与处理器基础实验-Four successive carry adder verilog implementation. Tb.v attached file. SCM development, digital logic and processor basic experiment
8weijiafaqi
- 8位加法器的verilog实现。VHDL，单片机开发程序，数字逻辑与处理器基础实验，你懂d。-8 adder verilog implementation. VHDL, MCU development program, the digital logic and processor basic experiment, you know d.
Area-Delay-Power-Efficient-Carry-Select-Adder-usi
- Implementation of IEEE 2015 paper for Area–Delay–Power Efficient Carry-Select Adder using VLSI verilog .The code tested by modelsim and also main program is test.v . If have any trouble mail to anandg.embedd@gmail.com-Implementation of IEEE 2015 pape
4bitadderkoggestone
- Kogge stone adder implementation in verilog
Task1_WithCLK
- half adder with verilog coding for
verilog四则运算器
- verilog四则运算，包括加法器、乘法器、除法器，不过都是拾人牙慧，整理一下，供新手参考。(Verilog four operations, including the adder, multiplier and divider, but are written, tidy, for novice reference.)
gray_counter
- 格雷码计数器实质包含了三个部分 格雷码转二进制、加法器、二进制转格雷码。通过quartus II 自带的Modlesim仿真验证了 能够实现二进制和格雷码之间的转换(Gray counter essence contains three parts, gray code to binary adder, binary gray code conversion. Modlesim simulation by quartus with II verified to achieve the conve
Verilog codes
- IT IS A CARRY S ELECT ADDER TO IMPROVE PERFORMANCE.
Fixed-Floating-Point-Adder-Multiplier-master
- Fixed-Floating-Point-Adder-Multiplier with test bench
lab0_32
- 大学生专业课的lab，用Verilog实现半加器(the necessary lab for college students to fulfill the function of half-adder)