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cpld11245
- 主要介绍了等精度频率测量原理，该原理具有在整个测试频段内保持高精度频率 测量的优点 同时在该原理基础上，采用了Verilog HDL语言设计了高速的等精度测频 模块，并且利用EDA开发平台QUARTUS11 3 .0对CPLD芯片进行写人，实现了计数等 主要逻辑功能 还使用C语言设计了该等精度频率计的主控程序以提高测量精度。本设 计实现了对频率变化范围较大的信号进行频率测量，能够满足高速度、高精度的测频要 求。-Introduced, such as the accuracy
sdram_all
- sdram 控制器的verilog 实现，包括用户逻辑和控制器的设计-SDRAM controller Verilog realization, including user logic and controller design
VerilogHDL
- 本文主要分析了FIR数字滤波器的基本结构和硬件构成特点,简要介绍了FIR滤波器实现的方式优缺点 结合Altera公司的Stratix系列产品的特点,以一个基于MAC的8阶FIR数字滤波器的设计为例,给出了使用Verilog硬件描述语言进行数字逻辑设计的过程和方法,并且在QuartusⅡ的集成开发环境下编写HDL代码,进行综合 利用QuartusⅡ内部的仿真器对设计做脉冲响应仿真和验证。-This paper analyzes the FIR digital filter structure an
hdlc_latest.tar
- HDLC在通讯设备中占有重要地位，本文件提供了完整正确的HDLC的硬件逻辑设计！对设计和学习都具有参考价值-HDLC in the communications equipment plays an important role, this document is to provide a complete hardware HDLC correct logic design! Design and learning have a reference value
Multi_Cycle_Microprocessor_with_Control
- Multi Cycle processor with control logic Verilog Computer organization and design
traffic
- 实现路*通灯系统的控制方法很多，可以用标准逻辑器件，可编程控制器PLC，单片机等方案来实现。但是这些控制方法的功能修改及调试都需要硬件电路的支持，在一定程度上增加了功能修改及系统调试的困难。因此，在设计中采用EDA技术，应用目前广泛应用的Verilog HDL硬件电路描述语言，实现交通灯系统控制器的设计，利用MAX+PLUS 集成开发环境进行综合、仿真，并下载到CPLD可编程逻辑器件中，完成系统的控制作用。-Intersection traffic signal systems to ach
DE2_NIOS_HOST_MOUSE_VGA
- 显示控制电路是整个场序彩色显示【15】【16】系统的心设计部分,本文采用Verilog HDL来设计。首先编写对各单元电路进行以行为级描述的Verilog代码,再用EDA工具对Verilog HDL代码进行功能仿真和逻辑综合。-Display control circuit is the field sequential color display 【15】 【16】 system design part of the heart, this paper Verilog HDL to desig
4-ahead_Adder
- 用Verilog HDL语言实现超前进位加法器的逻辑功能,通过ModelSim软件对4位超前进位加法器设计的仿真.-With the Verilog HDL language-ahead adder logic functions, by ModelSim software 4-ahead adder design simulation.
BouncingBall
- 桌面弹球实验的逻辑,SOPC 实验课的，使用 Verilog语言编写-the logic of bouncingball,Using Verilog HDL
Basic-sequential-logic
- 用Verilog语言实现D触发器、累加器的功能-D flip-flop, the function of the accumulator using Verilog language
my_encode
- 利用verilog语言对一个编码器进行RTL的描述，实现编码器的逻辑功能。-RTL descr iption of an encoder verilog language, the encoder logic functions.
alu.v
- a well written and yet small verilog hardware descr iption language or popularly known as simply Verilog program for an Arithmetic and Logic Unit or as popularly called ALU
verilog_stand_cell_lib
- verilog 门级设计及仿真标准单元库，包含142个基本的逻辑门单元。可用于VERILOG开发实现与或非、加法、减法、累加等基本的逻辑运算单元，实现精确的逻辑仿真。-verilog gate-level design and simulation of a standard cell library contains 142 basic logic gate unit. VERILOG implementation and can be used to develop or, addition
ver-1.3.36-14
- 大名鼎鼎gtk wave，不是应用软件， 是源代码。 Wave viewer for Verilog simulation. Keywords: Verilog, digital, logic, testing, wave viewer, VCD, LXT, LXT2, VZT, GHW, FST, scope, visualization, VHDL, Tcl-Wave viewer for Verilog simulation. Keywords:
blif2verilog-v1.2
- 将BLIF（Berkeley Logic Interchange Format）格式的电路转换为verilog代码，使用perl编写，需要perl环境才能使用。 内含BLIF格式的官方说明。-Translate BLIF（Berkeley Logic Interchange Format）circuit to verilog descr iption, the translator need perl environment to run. Please check you have rel
fifo_verilog
- 16位FIFO的硬件电路，使用verilog实现。文件内含组合逻辑和寄存逻辑两种方法的实现，以及对应的testbench测试代码-16 FIFO hardware circuits using verilog implementation. File contains a combination of logic and storage logic to achieve the two methods, and the corresponding testbench test code
4weizhucijinweijiafaqi_verilog
- 四位逐次进位加法器的verilog实现。附tb.v文件。单片机开发，数字逻辑与处理器基础实验-Four successive carry adder verilog implementation. Tb.v attached file. SCM development, digital logic and processor basic experiment
8weijiafaqi
- 8位加法器的verilog实现。VHDL，单片机开发程序，数字逻辑与处理器基础实验，你懂d。-8 adder verilog implementation. VHDL, MCU development program, the digital logic and processor basic experiment, you know d.
erxuanyiduoluxuanzeqi_no_maoxian
- 二选一多路选择器的verilog实现。VHDL，单片机开发程序，数字逻辑与处理器基础实验，你懂d。-Choose one multiplexer selector verilog implementation. VHDL, MCU development program, the digital logic and processor basic experiment, you know d.
jeas_reversable-vedic-multiplier
- reversible logic is mainly used to achieve low power. peres gate HUG gate is used to design a vedic multiplier. reversible gate we can give n numbers of input and we can get n number of output