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mips_project
- 我用verilog写的risc指令集的mips的cpu。可以支持定点运算。顶层单元是top。-I used to write verilog mips risc instruction set of the cpu. To support fixed-point arithmetic. Top-level unit is the top.
cputest.rar
- 自己刚写的一个RISC的cpu，位宽16，主要是测试其中的逻辑，数据宽度是一位，可以很容易扩展,Writing just one of their own RISC the cpu, bit 16, are testing one of the main logic, data width, a, can be easily extended
RiscCpu
- Verilog-RISC CPU 代码 实现了简单的RISC cpu，可供初学者参考，学习硬件描述语言，及设计方法。该程序通过了modelsim仿真验证。 北航-Verilog-RISC CPU code to achieve a simple RISC cpu, a reference for beginners to learn the hardware descr iption language, and design methods. The procedure adopted
risc
- 基于quartus II软件 用verilog 语言描述的精简指令CPU-quartus II verilog
Jh_cpu
- Jh_cpu is a cpu with 12 address,8 data bus, adn give direct address ,indirect address two addressin way.-This VHDl code can provide a total clear and detail process to create a basic function risc cpu.
computer1
- 一种RISC结构8位微控制器的设计与实现-The structure of a RISC micro-controller' s 8 Design and Implementation
computer2
- 一款8位RISC MCU的设计-An 8-bit RISC MCU Design .........
ley
- risc spm 自定义指令集及测试程序-custom risc instruction set and test procedures
SLC1657
- The Silicore SLC1657 is an eight-bit RISC microcontroller. It is delivered as a VHDL1 soft core2 module, and is intended for use in both ASIC and FPGA type devices. It is useful for microprocessor based embedded control applications such a
MANIK
- MANIK is a 32 bit RISC Microprocessor. The salient features of the processor are listed below. Features Hardware Features • Data Path Width 32 bits, with Four stage pipeline. • Mixed 16/32 bit instructions for code density ̶
cn_mega16-16L
- MEGA16-16L型号的中文说明资料，里面介绍RISC 结构，JTAG 接口，外设特点，I/O 和封装，特殊的处理器特点-MEGA16-16L models explanatory information in Chinese, which introduced the RISC architecture, JTAG interface, peripheral features, I/O and packaging, special features of the processor, and
arch
- emulator of RISC - architecture
PipelineCPU
- Quartus II 7.2环境中，采用硬件描述语言VHDL独立完成了基于MIPS指令集的32位RISC处理器的逻辑设计-quartusII mips pipeline 32bit cpu design
cpu
- 包括1) 时钟发生器 2) 指令寄存器 3) 累加器 4) RISC CPU算术逻辑运算单元 5) 数据控制器 6) 状态控制器 7) 程序计数器 8) 地址多路器 -1) clock generator 2) instruction register 3) accumulator 4) RISC CPU arithmetic logical unit 5) of the data controller 6) state controller 7),
RISCMCU_Presentation
- presentation for risc processor
risc
- RISC是一种执行较少类型计算机指令的微处理器，起源于80 年代的MIPS主机（即RISC 机），RISC机中采用的微处理器统称RISC处理器。这样一来，它能够以更快的速度执行操作（每秒执行更多百万条指令，即MIPS）。因为计算机执行每个指令类型都需要额外的晶体管和电路元件，计算机指令集越大就会使微处理器更复杂，执行操作也会更慢。 -RISC is a microprocessor performs fewer types of computer instructions, originat
risc_cpu
- SystemC实现的一个精简指令CPU模型-risc CPU model in systemc
risc-4-way-lru-processor-verilog
- A RISC processor written in verilog codes.
RISC
- A compiler to realize some of the RISC-V instructions.
cpusim
- C++模拟实现单线程CPU运行RISC-V指令集(C++ Simulated Implementation of RISC-V Instruction Set in Single Thread CPU)