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manchester_base_on_verilog
- yon用硬件描述语言写的曼彻斯特编解码,并在Xilinx CPLD上的实现,内容齐全,是学习的好资料-yon hardware descr iption language used to write the Manchester encoding and decoding Xilinx CPLD and the realization that the complete study is a good information
uart_fpga4fun
- rs232通信代码，在自己的xilinx开发板上已验证通过-rs232 code with verilog has been verified
uart
- 串口通讯rs232,时钟频率为40Mhz,波特率为19200,没有奇偶校验,在xilinx XC3S200A板子上验证过.-Serial communication rs232, clock frequency of 40Mhz, the baud rate to 19200, no parity, in the board on xilinx XC3S200A verified.
pro104_uart
- uart的代码，经实际运行可以通信，是xilinx uart 代码的改进，网上的xilinx uart代码有很多bug，用此代码可以改进运行。-UART code, the actual operation can be communication, xilinx uart code are improved, xilinx uart code online has a lot of bug, the code can be improved with this operation.
Lab10_RS232_ise10migration
- 串口传输,通过XILINX FPGA使用串口进行数据的接收和发送-RS232
SerialPort
- 一个用verilog HDL 编写的串口发送程序，可以下载到FPGA中。已经在ActelFPGA中试过了，很好用。稍微修改之后，可以与Xilinx和Altera公司的FPGA兼容。-A programe dialogue to transmit a serial data which is writen by Verilog HDL.
high_speed_data_recovery
- 1. 程序的功能是:高速串行数据的恢复. 2. 其基本原理是：利用过采样，检测串行数据的边沿跳变，然后根据边沿提取处在数据相位正中央相邻的抽样值，将串行数据恢复过来。 3. 此程序是verilog 语言编写，用于xilinx virtexE 系列的FPGA-1. Program functions are: high-speed serial data recovery. 2. The basic principle is: the use of over-sampling to det
HDLC_VHDL
- 用VHDL实现从以太网到并行数据以及从并行数据到以太网的HDLC成帧解帧.附详细代码说明,方便阅读.可方面移植到Altera及Xilinx等厂家芯片,是做基于FPGA的以太网设计的好资料-Achieved using VHDL and parallel data from the Ethernet to parallel data from the HDLC framing solution to Ethernet frames. Attached detailed code instructi
fpga_mcu_uart
- 用FPGA 开发板 SPARTAN3实现的串口程序，用XILINX 自带的ip核 -Achieved with the FPGA development board SPARTAN3 serial program that comes with the ip nuclear XILINX
uart
- Code VHDL/Verilog for UART FPGA: Xilinx, Altera-Code VHDL/Verilog for UART FPGA: Xilinx, Altera...
paixufahanshu
- TD-SCDMA的长期演进TD-LTE。为减轻TD-LTE综测仪开发中调试的复杂性，通过研究分析TD-LTE系统原语，提出了一种基于DSP TMS320C6455和FPGA 5vsx95tff1136(Xilinx)芯片的原语追踪平台。-Long-term evolution of TD-SCDMA, TD-LTE. TD-LTE system primitives through research and analysis in order to reduce the complexity o
SPI
- Verilog 代码的SPI接口，Xilinx器件-Verilog code about SPI
xuartps_polled_example
- xilinx zynq7000 串口调试程序-xilinx zynq7000 serial
groundhog_v_0_2
- Groundhog implements a SATA host bus adapter.-Groundhog implements a SATA host bus adapter. This Verilog-based project creates an easy-to-use interface between a user circuit on a Xilinx FPGA and a SATA hard drive or SSD.
my_spi_done
- Xilinx EDK开发 通过FPGA实现SPI通信-DK Xilinx development through SPI to achieve FPGA communication
Xilinx 6 Family4
- a service that allows to receive email at a temporary address that self-destructed after a certain time elapses. It is also known by names like : tempmail, 10minutemail, throwaway email, fake-mail or trash-mail. Many forums