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cosinexp
- 基于DSP的产生余弦信号的用C编写的程序，可通过CCS平台下载到DSK板上实现信号输出。-DSP-based cosine signals generated C preparation procedures, CCS platform can be downloaded to DSK board signal output.
DSPcorrelation
- 相关算法的应用很广，例如噪声中信号的检测，一个信号经过一段延迟后自身的相似性，信号中隐含周期性的检测，信号相关性的检验，信号时延长度的测量，滤除确定性信号中的随机干扰信号等等。相关函数还是描述随机信号的重要统计量。 利用CCS5000的集成开发平台，通过C语言对一正弦信号和一余弦信号进行了相关算法设计、编程和分析，然后将其置于CCS集成开发环境下,编译、调试、运行.-correlation algorithm used widely, such as noise signal detecti
coswave
- DSP5402产生余弦信号以C语言源代码,已仿真通过-DSP5402 cosine signals to produce C language source code, through simulation
cordic.rar
- 基于cordic算法的正余弦信号发生器，通过编译仿真,Cordic algorithm is based on the cosine signal generator, through the compiled simulation
cossin
- 数字信号源，输出不同频率，相位的正余弦信号，-Digital signal source, the output of different frequency, phase is the cosine signal,
DDS
- 本代码可以用于产生正余弦信号波形，利用FPGA内部的ROM放置一个正余弦采样点的数据表格，通过循环取址的方法，实现波形连续输出。-This code can be used to generate positive cosine signal waveforms, using FPGA' s internal ROM to place a sampling point is the cosine of the data tables, the circulation method of t
cosinexp
- 通过计算法制造出余弦信号，通过了CCSTMS320C5400的测试-By calculating the rule of law Zaochu cosine signal, passed the test CCSTMS320C5400
DDS
- 这是一个任意频率的正弦信号发生器，具有可改变输出信号频率，输出信号相位，任意转换输出信号类型（正弦、余弦、锯齿波、方波），屏幕可分别显示用户设定的信号频率与输出信号检测频率。-This is an arbitrary frequency sinusoidal signal generator, with can change the output signal frequency, the output signal phase, arbitrary conversion output sign
cordic
- 该程序使用Verilog语言，可以生成dds正余弦信号-The program uses the Verilog language, can generate sine and cosine signals dds
dds
- 用Verilog语言实现基于dds技术的余弦信号发生器，其输出位宽为16比特-Dds with the Verilog language technology based on the cosine signal generator, the output bit width is 16 bits
dsp_cose
- DSP的余弦信号产生程序，在CCS下通过-Cosine signal generation DSP program adopted under the CCS
DDS
- Verilog语言实现基于DDS技术的余弦信号发生器，输出位宽16Bit-Verilog language technology based on the cosine DDS signal generator, the output bit width 16Bit
ddsforsinandcos
- 利用VerilogHDL调用MATLAB产生的数据实现基于DDS技术的正余弦信号发生器，输出位宽为16。-Using the data generated VerilogHDL call MATLAB implementation is based on DDS technology cosine signal generator, the output is 16 bits wide.
myfft
- fft信号发生，产生连续的余弦信号，分别用C语言编写-fft signal, resulting in continuous cosine signals, respectively, with C language
NCO
- 是数控振荡器的程序，能够产生正弦和余弦信号，是上、下变频技术的主要步骤-NCO of the program is capable of generating sine and cosine signals, is on the main steps of down-conversion technology
cordic
- 用verilog实现的一个基于流水线结构的正余弦信号发生器，六级流水线-Verilog realize a pipeline structure of the sine and cosine signal generator , six pipeline
DDS
- 基于FPGA的DDS信号发生器，实现简单的余弦信号输出- 基于FPGA的DDS信号发生器，实现简单的余弦信号输出
5-15
- 用verilog语言实现基于DDS技术的余弦信号发生器，其输出位宽为16比特-Verilog language cosine signal generator based on DDS technology, the output bit width is 16 bits
5-17
- 用verilog实现一个基于流水线结构的正、余弦信号发生器-Based on Pipeline Structure verilog to achieve a sine and cosine signal generator
AD9854P430
- 使用市场上现在广泛应用的AD9854芯片和MSP430单片机进行DDS模块的制作，整个程序使用并行数据传输，能稳定输出0-60M的正余弦信号，可根据需要改变输出信号的幅值-Now on the market and widely used MSP430 microcontroller chip AD9854 DDS module production, the entire program using parallel data transmission, can stabilize outpu